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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is
	port(A: in STD_LOGIC;
	     B: in STD_LOGIC;
	     C: in STD_LOGIC;
		Sum: out STD_LOGIC;
	       carry: out STD_LOGIC);
	end Full_Adder;


architecture Behavioral of Full_Adder is 
begin
Sum<= A XOR B XOR C;
carry<= (A and B) or ((A xor B) and C);

end Behavioral;
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