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\\priority encoder
module priority_encoder_4_2(input [3:0] in, output reg [1:0] out);
always @* begin
case(in)
4'b0001: out = 2'b00;
4'b0010: out = 2'b01;
4'b0100: out = 2'b10;
4'b1000: out = 2'b11;
4'b1111: out = 2'b11;
default: out = 2'b00;
endcase
end
endmodule
module testbench_priority_encoder;
reg [3:0] in;
wire [1:0] out;
Test bench for 4X2 encoder
priority_encoder_4_2 encoder_inst(.in(in), .out(out));
initial begin
$monitor("in=%b, out=%b", in, out);
in = 4'b0000; #10;
in = 4'b0001; #10;
in = 4'b0010; #10;
in = 4'b0100; #10;
in = 4'b1000; #10;
in = 4'b1111; #10;
in = 4'b1010; #10;
$finish;
end
end module
\\binary multiplier
module multiplier_4x4(P,A,B);
input [3:0]A,B;
output [7:0]P;
wire [23:1]W;
and a1(P[0],A[0],B[0]);
and a2(W[1],A[1],B[0]);
and a3(W[2],A[2],B[0]);
and a4(W[3],A[3],B[0]);
and a5(W[4],A[0],B[1]);
and a6(W[5],A[1],B[1]);
and a7(W[6],A[2],B[1]);
and a8(W[7],A[3],B[1]);
and a9(W[8],A[0],B[2]);
and a10(W[9],A[1],B[2]);
and a11(W[10],A[2],B[2]);
and a12(W[11],A[3],B[2]);
and a13(W[12],A[0],B[3]);
and a14(W[13],A[1],B[3]);
and a15(W[14],A[2],B[3]);
and a16(W[15],A[3],B[3]);
adder_4bit PA1({W[18],W[17],W[16],P[1]},W[19],{1'b0,W[3],W[2],W[1]},{W[7],W[6],W[5],W[4]});
adder_4bit PA2({W[22],W[21],W[20],P[2]},W[23],{W[19],W[18],W[17],W[16]},{W[11],W[10],W[9],W[8]});
adder_4bit PA3({P[6],P[5],P[4],P[3]},P[7],{W[23],W[22],W[21],W[20]},{W[15],W[14],W[13],W[12]});
endmodule
"Adder 4-bit code":
module adder_4bit(s,cout,a,b);
input [3:0]a;
input [3:0]b;
output [3:0]s;
output cout;
wire[3:1]c;
full_adder FA0(a[0],b[0],1'b0,s[0],c[1]);
full_adder FA1(a[1],b[1],c[1],s[0],c[1]);
full_adder FA2(a[2],b[2],c[2],s[2],c[3]);
full_adder FA3(a[3],b[3],c[3],s[3],cout);
endmodule
NOTE : Make full adder for this...
"Test bench":
module multiplier_4x4_tb;
reg [3:0]A;
reg [3:0]B;
wire [7:0]P;
multiplier_4x4 uut(.P(P),.A(A),.B(B));
initial begin
A=13;B=11;#100;
A=10;B=11;#100;
end
endmodule
\\comparator
module comparator(Data_in_A,Data_in_B,less,equal,greater);
input [3:0]Data_in_A;
input [3:0]Data_in_B;
output less,equal,greater;
reg less,equal,greater;
always@(Data_in_A or Data_in_B)
begin
if(Data_in_A>Data_in_B)
begin
less=0;
equal=0;
greater=1;
end
else if(Data_in_A==Data_in_B)
begin
less=0;
equal=1;
greater=1;
end
else
begin
less=1;
equal=0;
greater=0;
end
end
endmodule
\\SR flip flop
module sr_ff_beh(S,R,CLK,RST,Q,Qbar);
output Q,Qbar;
input S,R,CLK,RST;
reg Q;
always @(posedge CLK)
begin
if (!RST)
Q <= 1'b0;
else
Q <= (S)|(~R & Q);
end
assign Qbar = ~ Q ;
endmodule
"""Test bench:"""
module sr_ff_test;
reg S,R,CLK;
wire Q,Qbar;
sr_ff_beh
sr_ff_test(S,R,CLK,Q,Qbar);
initial
begin
forever
begin
CLK=1;
#50 CLK=0;
#50 CLK=1;
end
end
initial
begin
S=0;R=1;
#100 S=0;R=0;
#100 S=1;R=0;
#100 S=1;R=1;
end
initial
begin
$monitor($time,"S=%b,R=%b,CLK=%b,Q=%b,Qbar=%b",S,R,CLK,Q,Qbar);
end
endmodule
\\JK FLIP FLOP
module jk_ff_beh(J,K,CLK,RST,Q,Qbar);
output Q,Qbar;
input J,K,CLK,RST;
reg Q;
always @(posedge CLK)
begin
if (!RST)
Q <= 1'b0;
else
Q <= (J & ~Q)|(~K & Q);
end
assign Qbar = ~ Q ;
endmodule
"""Test bench"""
module jk_ff_test;
reg J,K,CLK;
wire Q,Qbar;
jk_ff_beh jk_ff_test(J,K,CLK,Q,Qbar);
initial
begin
forever
begin
CLK=1;
#50 CLK=0;
#50 CLK=1;
end
end
initial
begin
#000 J=0;K=1;
#100 J=0;K=0;
#100 J=1;K=0;
#100 J=1;K=1;
end
initial
begin
$monitor($time,"J=%b,K=%b,CLK=%b,Q=%b,Qbar=%b",J,K,CLK,Q,Qbar);
end
endmodule
\\D flip flop
module d_ff_beh(D,CLK,RST,Q,Qbar);
output Q,Qbar;
input D,CLK,RST;
reg Q;
always @(posedge CLK)
begin
if (!RST)
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q ;
endmodule
"""Test bench"""
module d_ff_test;
reg D,CLK;
wire Q,Qbar;
d_ff_beh
d_ff_test(D,CLK,Q,Qbar);
initial
begin
forever
begin
CLK=1;
#50 CLK=0;
#50 CLK=1;
end
end
initial
begin
D=0;
#100 D=1;
end
initial
begin
$monitor($time,"D=%B,CLK=%b,Q=%b,Qbar=%b",D,CLK,Q,Qbar);
end
endmodule
T FLIP FLOP
module t_ff_beh(T,CLK,RST,Q,Qbar);
output Q,Qbar;
input T,CLK,RST;
reg Q;
always @(posedge CLK)
begin
if (!RST)
Q <= 1'b0;
else
Q <= T^Q;
end
assign Qbar = ~ Q;
endmodule
"""Test bench"""
module t_ff_test;
reg T,CLK;
wire Q,Qbar;
t_ff_beh
t_ff_test(T,CLK,Q,Qbar);
initial
begin
forever
begin
CLK=1;
#50 CLK=0;
#50 CLK=1;
end
end
initial
begin
T=0;
#100 T=1;
end
initial
begin
$monitor($time,"T=%B,CLK=%b,Q=%b,Qbar=%b",T,CLK,Q,Qbar);
end
endmodule
PISO CODE:
module PISO(clk,d,q,shift_load);
input clk,shift_load;
input[3:0]d;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk)
begin
if(shift_load==1'b0)
begin
q<=1'b0;
temp<=d;
end
else
begin
q<=temp[0];
temp<=temp>>1'b1;
end
end
endmodule
""""Test bench""""
module PISO_tb;
reg clk,shift_load;
reg [3:0]d;
wire q;
PISO uut(.clk(clk),.d(d),.q(q),.shift_load(shift_load));
initial clk=1'b1;
always #100 clk=~clk;
initial begin
d=4'b1101; shift_load=1'b0;
#200;
shift_load=1'b1;
#200;
d=4'b1001;shift_load=1'b0;
#200;
shift_load=1'b1;
#1000 $stop;
end
endmodule
1:4 demux:
module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in;
input s0;
input s1;
output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule
2x4 decoder:
module decoder_2_to_4( input a0, input a1, output d0, output d1, output d2, output d3);
not g1(an0,a0);
not g2(an1,a1);
and(d0,an0,an1);
and(d1,a0,an1);
and(d2,an0,a1);
and(d3,a0,a1);
endmodule
4:1 mux:
module mux4to1(i0,i1,i2,i3,s0,s1,out);
input i0,i1,i2,i3;
output out;
wire w1,w2;
wire y0,y1,y2,y3;
not(w1,s1);
not(w2,s0);
and(y0,i0,w1,w2);
and(y1,i1,w1,s0);
and(y2,i2,s1,w2);
and(y3,i3,s1,s0);
or(out,y0,y1,y2,y3);
endmodule
D flip flop with reset signal:
module d_ff_bh (rst_n, clk, d, q);
input rst_n, clk, d;
output q;
wire rst_n, clk, d;
reg q;
always @ (rst_n or posedge clk)
begin
if (rst_n == 0)
q <= 1'b0;
else q <= d;
d_ff_bh inst1 (rst_n, clk, x1, y[1]);
//instantiate flip-flop y[2]
d_ff_bh inst2 (rst_n, clk, y[1], y[2]);
//instantiate flip-flop y[3]
d_ff_bh inst3 (rst_n, clk, y[2], y[3]);
//instantiate flip-flop y[4]
d_ff_bh inst4 (rst_n, clk, y[3], y[4]);
//define outputs z1, z2, z3, and z4
assign z1 = y[1],
z2 = y[2],
Code:
module srff(q,q1,s,r,clk);
output q,q1;
input s,r,clk;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk)
begin
case ({s,r})
{1'b0,1'b0}:begin q<=q;q1<=q1;end
{1'b0,1'b1}:begin q<=0;q1<=1;end
{1'b1,1'b0}:begin q<=1;q1<=0;end
{1'b1,1'b1}:begin q<=1'bx;q1<=1'bx;end
endcase
end
endmodule
Test Bench
module testbench();
// Inputs
reg s;
reg r;
reg clk;
// Outputs
wire q;
wire q1;
// Instantiate the Unit Under Test (UUT)
srff uut (
.q(q),
.q1(q1),
.s(s),
.r(r),
.clk(clk)
);
initial
begin
$monitor($time,"s=%b,r=%b,q=%b,q1=%b",s,r,q,q1);
clk=1'b0;
#10 clk=~clk;
// Initialize Inputs
s = 0;
r = 0;
clk = 1;
// Wait 100 ns for global reset to finish
#100;
s = 0;
r = 1;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
s = 1;
r = 0;
clk = 1;
#100;
s = 1;
r = 1;
clk = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule
# Adder/Subtractor code
module adder_bar_subtractor(S, C, V, A, B, m);
output [3:0] S; // The 4-bit sum/difference.
output C; // The 1-bit carry/borrow status.
output V; // The 1-bit overflow status.
input [3:0] A; // The 4-bit augend/minuend.
input [3:0] B; // The 4-bit addend/subtrahend.
input m; // The operation: 0 => Add, 1=>Subtract.
wire C0; // The carry out bit of fa0, the carry in bit of fa1.
wire C1; // The carry out bit of fa1, the carry in bit of fa2.
wire C2; // The carry out bit of fa2, the carry in bit of fa3.
wire C3; // The carry out bit of fa2, used to generate final carry/borrrow.
wire B0; // The xor'd result of B[0] and m
wire B1; // The xor'd result of B[1] and m
wire B2; // The xor'd result of B[2] and m
wire B3; // The xor'd result of B[3] and m
// Looking at the truth table for xor we see that
// B xor 0 = B, and
// B xor 1 = not(B).
// So, if m==1 means we are subtracting, then
// adding A and B xor m alog with setting the first
// carry bit to m, will give us a result of
// A+B when m==0, and A+not(B)+1 when Op==1.
// Note that not(B)+1 is the 2's complement of B, so
// this gives us subtraction.
xor(B0, B[0], m);
xor(B1, B[1], m);
xor(B2, B[2], m);
xor(B3, B[3], m);
xor(C, C3, m); // Carry = C3 for addition, Carry = not(C3) for subtraction.
xor(V, C3, C2); // If the two most significant carry output bits differ, then we have an overflow.
full_adder fa0(S[0], C0, A[0], B0, m); // Least significant bit.
full_adder fa1(S[1], C1, A[1], B1, C0);
full_adder fa2(S[2], C2, A[2], B2, C1);
full_adder fa3(S[3], C3, A[3], B3, C2); // Most significant bit.
endmodule // ripple_carry_adder_subtractor
module full_adder(S, Cout, A, B, Cin);
output S;
output Cout;
input A;
input B;
input Cin;
wire w1;
wire w2;
wire w3;
wire w4;
xor(w1, A, B);
xor(S, Cin, w1);
and(w2, A, B);
and(w3, A, Cin);
and(w4, B, Cin);
or(Cout, w2, w3, w4);
endmodule // full_adder
4bit addersubtractor::
module full_adder_bip (a, b, cin, sum, cout);
//define inputs and outputs
input a, b, cin;
output sum, cout;
//design the full adder
//design the sum
xor inst1 (net1, a, b);
and inst2 (net2, a, b);
xor inst3 (sum, net1, cin);
//define the carry-out
and inst4 (net3, net1, cin);
or inst5 (cout, net3, net2);
endmodule
module adder4_ripple_carry (a, b, cin, sum, cout);
input [3:0] a, b; //define inputs and outputs
input cin;
output [3:0] sum;
output cout;
//define internal nets
wire [3:0] c;
//define output
assign cout = c[3]; //continued on next page
//design the ripple-carry adder
//instantiating the full adders
full_adder_bip inst0 (a[0], b[0], cin, sum[0], c[0]);
full_adder_bip inst1 (a[1], b[1], c[0], sum[1], c[1]);
full_adder_bip inst2 (a[2], b[2], c[1], sum[2], c[2]);
full_adder_bip inst3 (a[3], b[3], c[2], sum[3], c[3]);
endmodule
EX :2 Behavioural Model
module adder4 (a, b, cin, sum, cout);
//define inputs and outputs
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
//variables are reg in always
reg [3:0] sum;
reg cout;
//perform the sum and carry-out operations
always @ (a or b or cin)
begin
sum = a + b + cin;
cout = (a[3] & b[3]) |
((a[3] | b[3]) & (a[2] & b[2])) |
((a[3] | b[3]) & (a[2] | b[2]) & (a[1] & b[1])) |
((a[3] | b[3]) & (a[2] | b[2]) & (a[1] | b[1])
& (a[0] & b[0])) |
((a[3] | b[3]) & (a[2] | b[2]) & (a[1] | b[1])
& (a[0] | b[0]) & cin);
end
endmodule
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