WEEK1

module TB;
reg aa,bb,cc;
wire ss,cy;
fulladd add1(.a(aa), .b(bb), .cin(cc), .s(ss), .cout(cy));
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end

initial begin $monitor(aa,bb,cc,ss,cy);
aa = 1'b0;
bb = 1'b0;
cc=1'b0;
#5
aa = 1'b0;
bb = 1'b1;
cc=1'b1;
#5
aa = 1'b1;
bb = 1'b0;
cc=1'b0;
#5
aa = 1'b1;
bb = 1'b1;
cc=1'b0;
#5
aa = 1'b0;
bb = 1'b0;
cc=1'b1;
end
endmodule

//

module fulladd(input wire a, b, cin, output wire s, cout);
	assign s = (a^b)^cin;
	assign cout = (a&b) | (a&cin) | (b&cin);
	endmodule

//

module faddd(input wire [3:0] a, b, input wire cin, output wire [3:0] s, output wire cout);
wire [2:0] c;
fulladd f0(a0, b0, cin, s0, c0);
fulladd f1(a1, b1, c0, s1, c1);
fulladd f2(a2, b2, c1, s2, c2);
fulladd f3(a3, b3, c2, s3, cout);
endmodule