DigitSeparator

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vhdl
2 years ago
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----------
--LOGIKA--
----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------
--                  SEPARÁTOR ČÍSLIC                       --
-------------------------------------------------------------

entity DigitSeparator is
    port(
        value: in unsigned(6 downto 0);
        leastSingnificantDigit: out unsigned(3 downto 0);
        mostSignificantDigit: out unsigned(3 downto 0)
    );
end entity DigitSeparator;

architecture DigitSeparator of DigitSeparator is
begin
    -- Set the outputs to 1111 1111 if the input is greater than 99
    process(value)
    begin
        if value > 99 then
            leastSingnificantDigit <= "1111";
            mostSignificantDigit <= "1111";
        else
            leastSingnificantDigit <= value mod 10;
            mostSignificantDigit <= value / 10;
        end if;
    end process;
end architecture DigitSeparator;



--------------
--TEST BENCH--
--------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity DigitSeparatorTB is
end entity DigitSeparatorTB;

architecture DigitSeparatorTB of DigitSeparatorTB is
    component DigitSeparator
        port(
            value: in unsigned(6 downto 0);
            leastSingnificantDigit: out unsigned(3 downto 0);
            mostSignificantDigit: out unsigned(3 downto 0)
        );
    end component DigitSeparator;


    signal value: unsigned(6 downto 0) := "0110000";
    signal leastSingnificantDigit: unsigned(3 downto 0);
    signal mostSignificantDigit: unsigned(3 downto 0);


begin
    kaka: DigitSeparator port map (value, leastSingnificantDigit, mostSignificantDigit);
    value <= "0110000", "1111111" after 100 ns;
end architecture DigitSeparatorTB;