Untitled

module carry_lookahead_adder #(parameter WIDTH = 4) (
    input clk,
    input [WIDTH-1:0] i_add1,
    input [WIDTH-1:0] i_add2,
    output [WIDTH:0] o_result
);

    // Pipeline registers for inputs
    reg [WIDTH-1:0] add1_reg_stage1, add2_reg_stage1;
    // Pipeline registers for intermediate results
    reg [WIDTH-1:0] w_SUM_stage1, w_G_stage2, w_P_stage2;
    reg [WIDTH:0] w_C_stage2;

    wire [WIDTH-1:0] w_G, w_P, w_SUM;
    wire [WIDTH:0] w_C;

    // Stage 1: Register inputs
    always @(posedge clk) begin
        add1_reg_stage1 <= i_add1;
        add2_reg_stage1 <= i_add2;
    end

    // Create the Full Adders
    genvar ii;
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin
            assign w_SUM[ii] = add1_reg_stage1[ii] ^ add2_reg_stage1[ii] ^ w_C[ii];
        end
    endgenerate

    // Stage 2: Register sum
    always @(posedge clk) begin
        w_SUM_stage1 <= w_SUM;
    end

    // Create the Generate (G) Terms: Gi=Ai*Bi
    // Create the Propagate Terms: Pi=Ai+Bi
    // Create the Carry Terms
    genvar jj;
    generate
        for (jj = 0; jj < WIDTH; jj = jj + 1) begin
            assign w_G[jj] = add1_reg_stage1[jj] & add2_reg_stage1[jj];
            assign w_P[jj] = add1_reg_stage1[jj] | add2_reg_stage1[jj];
        end
    endgenerate

    assign w_C[0] = 1'b0; // no carry input on first adder

    // Stage 3: Compute carry terms
    generate
        for (jj = 0; jj < WIDTH; jj = jj + 1) begin
            always @(posedge clk) begin
                w_C[jj+1] <= w_G[jj] | (w_P[jj] & w_C[jj]);
            end
        end
    endgenerate

    // Stage 3: Register G, P, and C terms
    always @(posedge clk) begin
        w_G_stage2 <= w_G;
        w_P_stage2 <= w_P;
        w_C_stage2 <= w_C;
    end

    // Assign the final result
    assign o_result = {w_C_stage2[WIDTH], w_SUM_stage1}; // Verilog Concatenation

endmodule