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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lukas_bebee_wrapper is
Port (reset: in std_logic;
		enable: in std_logic;
		clk: in std_logic;
		HEX0: out std_logic_vector(6 downto 0);
		HEX5: out std_logic_vector(6 downto 0));
end lukas_bebee_wrapper;

architecture wrapper of lukas_bebee_wrapper is

	component lukas_bebee_clock_divider is
	Port (enable : in std_logic;
			reset : in std_logic;
			clk : in std_logic;
			en_out : out std_logic);
   end component;
	
	component ROM is
	Port (clk : in std_logic;
			reset : in std_logic;
			data : out std_logic);
	end component;
	
	component lukas_bebee_sequence_detector is
	Port (seq : in std_logic ;
			enable : in std_logic;
			reset : in std_logic;
			clk : in std_logic;
			cnt_1 : out std_logic_vector(2 downto 0); -- counts the occurrence of the pattern "1011".
			cnt_2 : out std_logic_vector(2 downto 0)); -- counts the occurrence of the pattern "0010".
	end component;
	
	component seven_segment_decoder is
	Port (code : in std_logic_vector (2 downto 0);
		   segments_out : out std_logic_vector(6 downto 0));
	end component;
	
	signal en_out : std_logic;
	signal data : std_logic;
	signal out_1 : std_logic_vector(2 downto 0);
	signal out_2 : std_logic_vector(2 downto 0);
	
begin 
		-- Set up clock divider for ROM and sequence counter
		clock_divider: lukas_bebee_clock_divider port map(enable, reset, clk, en_out);
		
		-- Set up ROM and sequence counter
		mem: ROM port map(en_out, reset, data); -- clock is en_out for fpga and clk for testbench
		sequence_detector: lukas_bebee_sequence_detector port map(data, enable, reset, en_out, out_1, out_2); -- clock is en_out for fpga and clk for testbench
		
		-- Outputs go into decoder
		decoder: seven_segment_decoder port map(out_1, HEX0);
		decoder2: seven_segment_decoder port map(out_2, HEX5);

end wrapper;

------------

--
-- entity name: g55_ARCCOS 
--
-- Version 1.0
-- Authors: Mohammad shaheer Bilal, Matthew Beaudet
-- Date: March 16 2023


library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- needed since you are using unsigned numbers

entity g55_ARCCOS is
port ( X : in std_logic_vector(7 downto 0);
CLOCK : in std_logic;
ANGLE : out std_logic_vector(9 downto 0));
end g55_ARCCOS;

architecture a of g55_ARCCOS is

signal xsignal, xd1, xd2, xd3, xd4, xd5 : unsigned(7 downto 0);
signal x2, x2d1, x2d2 : unsigned(15 downto 0);
signal p1, s1, p2, s2, p3, anglesignal : unsigned(31 downto 0);


begin
xsignal <= unsigned(x);

process(X, CLOCK)

begin

  if rising_edge(CLOCK) then
  
	x2 <= (xsignal*xsignal);
	p1 <= ((86*x2)/65536); 
	s1 <= (191 + p1);
	p2 <= resize(((s1*x2d2)/65536), 32);
	s2 <= resize((1144+p2),32);
	p3 <= resize(((s2*xd5)/512),32);
	anglesignal <= (900-p3);
	ANGLE <= std_logic_vector(anglesignal(9 downto 0));
	xd1 <= xsignal;
	xd2 <= xd1;
	xd3 <= xd2;
	xd4 <= xd3;
	xd5 <= xd4;
	x2d1 <= x2;
	x2d2 <= x2d1; --added hold registers. 
  end if;
 end process;
 end a;