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module Demux(Y0,Y1,Y2,Y3,S0,S1,D);

input S0, S1,D;

output Y0,Y1,Y2,Y3;

assign Y0 = D & (~S1) & (~S0);

assign Y1 = D & (~S1) & (S0);

assign Y2 = D & (S1) & (~S0);

assign Y3 = D & (S1) & (S0);

endmodule
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