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--  Test Bench
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;              

ENTITY tb_clkdiv_tst IS
END tb_clkdiv_tst;

ARCHITECTURE tb_arch of tb_clkdiv_tst IS

component clkdiv is
port (
  clk   : in std_logic;
  clkms: out std_logic
    );
end component;

--Signal Declaration
signal clk :std_logic;
signal clkms :std_logic;

begin
--Instantiate Design Under Test using Port Map.
uut:  clkdiv  PORT MAP (clk,clkms);
--clk
t_prcs_clk: PROCESS 
    BEGIN
        clk <= '0';
        wait for 10 ns;
         clk <= '1';
        wait for 10 ns;
    END PROCESS;
	 
end tb_arch;