register_file
unknown
verilog
a month ago
764 B
8
Indexable
module register_file( Clk , WEN , RW , busW , RX , RY , busX , busY ); input Clk, WEN; input [2:0] RW, RX, RY; input [7:0] busW; output [7:0] busX, busY; // write your design here, you can delcare your own wires and regs. // The code below is just an eaxmple template reg [7:0] r [0:7]; reg [7:0] r_nxt [1:7]; integer i; assign busX = r[RX]; assign busY = r[RY]; always @(*) begin for (i = 1; i < 8; i = i + 1) begin if (WEN && (RW == i)) begin r_nxt[i] = busW; end else begin r_nxt[i] = r[i]; end end end always@(posedge Clk) begin r[0] <= 8'b0; for (i = 1; i < 8; i = i + 1) begin r[i] <= r_nxt[i]; end end endmodule
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