sequential logic

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unknown
verilog
2 years ago
922 B
1
Indexable
Never
`include "global.v"
/*
`define STAT_PAUSE 1'b0
`define STAT_COUNT 1'b1
*/

module fsm(
    output count_en,
    output reset_en,
    output reg state,
    input start_pause,
    input reset,
    input clk,
    input rst_n
);

    reg next_state;

    // combinational
    always @* begin
        case (state)
            `STAT_PAUSE: begin
                next_state <= (start_pause) ? `STAT_COUNT : `STAT_PAUSE;
            end
            `STAT_COUNT: begin
                next_state <= (start_pause) ? `STAT_PAUSE : `STAT_COUNT;
            end
        endcase
    end

    // sequential 
    always @(posedge clk or negedge rst_n) begin
        if (~rst_n) begin
            state <= `STAT_PAUSE;
        end else begin
            state <= next_state;
        end
    end

    // output 
    assign count_en = (state == `STAT_COUNT);
    assign reset_en = reset;

endmodule