Untitled

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity automat is
 port(
   clk : in STD_LOGIC;
   reset : in STD_LOGIC;
	x1 : in STD_LOGIC;
   x2 : in STD_LOGIC;
	y1 : out STD_LOGIC;
   y2 : out STD_LOGIC;
   y3 : out STD_LOGIC
       );
end automat;

architecture automat_a of automat is 
type stan_type is (A0, A1, A4, A2, A3);

signal stan: stan_type;

begin

stan_machine: process(clk, reset)
begin
if reset = '1' then
stan <= A0;
elsif clk'event and clk = '1' then
case stan is
	when A0 =>
	if reset='1' then
	stan <- A0;
	elsif reset='0' then
	stan<=A1;
	end if;
	when A1 =>
	if x1='0'then
	stan <=A3;
	elsif x1='1' then
	stab => A2;
	end if;
	when A4 =>
	if reset = '1' then
	//
	elsif x2 = '0' and x1='1' then
	stan <= A2;
	elsif x2 = '1' then
	stan <= A4;
	end if;
	
when others =>
null;
end case;
end if;
end process;

y1_assignment;

y1 <= '1' when (stan = A1) else
		'0' when (stan = A4) else
		'0' when (stan = A2) else
		'0' when (stan = A3) else
		'0';

y2_assignment;

y2 <= '0' when (stan = A1) else
		'0' when (stan = A4) else
		'1' when (stan = A2) else
		'0' when (stan = A3) else
		'0';

		
y3_assignment;

y3 <= '0' when (stan = A1) else
		'0' when (stan = A4) else
		'0' when (stan = A2) else
		'1' when (stan = A3) else
		'1';


	
end automat;