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module N_bit_register #(parameter WIDTH = 4) (
    input clk,
    input [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
);
    always @(posedge clk) begin
        q <= d;
    end
endmodule

module pipelined_carry_lookahead_adder #(parameter WIDTH = 4) (
    input clk,
    input [WIDTH-1:0] i_add1,
    input [WIDTH-1:0] i_add2,
    output [WIDTH:0] o_result
);
    wire [WIDTH:0] w_C;
    wire [WIDTH-1:0] w_G, w_P, w_SUM;
    wire [WIDTH-1:0] w_SUM_stage1, w_SUM_stage2;
    wire [WIDTH:0] w_C_stage1, w_C_stage2;

    // Stage 1: Full Adders
    genvar ii;
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin
            assign w_SUM[ii] = i_add1[ii] ^ i_add2[ii] ^ w_C[ii];
        end
    endgenerate

    // Register to hold intermediate sum values
    N_bit_register #(WIDTH) reg_stage1 (.clk(clk), .d(w_SUM), .q(w_SUM_stage1));

    // Register to hold intermediate carry values
    N_bit_register #(WIDTH+1) reg_carry_stage1 (.clk(clk), .d(w_C), .q(w_C_stage1));

    // Stage 2: Generate and Propagate Terms
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin
            assign w_G[ii] = i_add1[ii] & i_add2[ii];
            assign w_P[ii] = i_add1[ii] | i_add2[ii];
        end
    endgenerate

    // Stage 3: Carry Terms
    generate
        for (ii = 0; ii < WIDTH; ii = ii + 1) begin
            assign w_C[ii + 1] = w_G[ii] | (w_P[ii] & w_C[ii]);
        end
    endgenerate

    // Register to hold intermediate carry values
    N_bit_register #(WIDTH+1) reg_carry_stage2 (.clk(clk), .d(w_C), .q(w_C_stage2));

    assign w_C[0] = 1'b0; // No carry input on first adder

    // Register to hold final sum values
    N_bit_register #(WIDTH) reg_stage2 (.clk(clk), .d(w_SUM_stage1), .q(w_SUM_stage2));

    assign o_result = {w_C_stage2[WIDTH], w_SUM_stage2}; // Verilog Concatenation

endmodule