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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Shifter is
    port (
        shift_lsl  : in  std_logic;
        shift_lsr  : in  std_logic;
        shift_asr  : in  std_logic;
        shift_ror  : in  std_logic;
        shift_rrx  : in  std_logic;
        shift_val  : in  std_logic_vector(4 downto 0);
        din        : in  std_logic_vector(31 downto 0);
        cin        : in  std_logic;
        dout       : out std_logic_vector(31 downto 0);
        cout       : out std_logic;
        vdd        : in  bit;
        vss        : in  bit
    );
end Shifter;

architecture Behavioral of Shifter is
begin
    process(shift_lsl, shift_lsr, shift_asr, shift_ror, shift_rrx, shift_val, din, cin)
    variable temp : unsigned(31 downto 0);
    variable carry_out : std_logic;
    begin
        -- Left Shift Logical (LSL)
        if shift_lsl = '1' then
            temp :=  shift_left(unsigned(din), to_integer( unsigned(shift_val)));
            carry_out := din(31 - to_integer(unsigned(shift_val)));
        -- Right Shift Logical (LSR)
        elsif shift_lsr = '1' then
            temp := unsigned(din) srl to_integer(unsigned(shift_val));
            carry_out := din(to_integer(unsigned(shift_val)) - 1);
        -- Right Shift Arithmetic (ASR)
        elsif shift_asr = '1' then
	--	if din(31)='1' then
          --  		temp := rotate_right(signed(din), to_integer(unsigned(shift_val)));
            --		carry_out := '1';
	--	else
                        temp := rotate_right(unsigned(din), to_integer(unsigned(shift_val)));
                        carry_out := din(to_integer(unsigned(shift_val)) - 1);
	--	end if;
        -- Rotate Right (ROR)
        elsif shift_ror = '1' then
            temp := unsigned(din) ror (to_integer(unsigned(shift_val)));
            carry_out := din(to_integer(unsigned(shift_val)) - 1);
        -- Rotate Right with Extend (RRX)
        elsif shift_rrx = '1' then
            temp := cin & unsigned(din(31 downto 1)); -- Rotation with carry input
            carry_out := din(0);
        else
            temp := unsigned(din);  -- Default case: no shift
            carry_out := '0';
        end if;

        dout <= std_logic_vector(temp);
        cout <= carry_out;
    end process;
end Behavioral;