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`timescale 1ns/1ps

module Parameterized_Ping_Pong_Counter (clk, rst_n, enable, flip, max, min, AN, seg);
input clk, rst_n;
input enable;
input flip;
input [3:0] max;
input [3:0] min;
reg direction;
reg [3:0] out;
output [3:0] AN;
output [6:0] seg;
reg [6:0] seg3, seg2, seg1, seg0;

wire one_pulse_flip, one_pulse_rst_n;
wire temp1, temp2;

debounce D1 (temp1, flip, clk);
onepulse O1 (temp1, clk, one_pulse_flip);
debounce D2 (temp2, ~rst_n, clk);
onepulse O2 (temp2, clk, one_pulse_rst_n);

AN_mux M1 (clk, seg3, seg2, seg1, seg0, seg, AN);

always @(posedge clk) begin
    if(one_pulse_rst_n == 1'b0) begin
        out <= min;
        direction <= 1'b1;
    end
    else if(enable == 1'b1 && max > min && out <= max && out >= min) begin
        if(one_pulse_flip == 1'b1) direction <= ~direction;
        if(out == max && direction == 1'b1) begin
            out <= out - 1'b1;
            direction <= 1'b0;
        end
        else if(out == min && direction == 1'b0) begin
            direction <= 1'b1;
            out <= out + 1'b1;
        end
        else if(direction == 1'b1) out <= out + 1'b1;
        else if(direction == 1'b0) out <= out - 1'b1;
    end
end

// 7-segment display
always @(*) begin
    if(out == 4'b0000) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0000001;
    end
    else if(out == 4'b0001) begin
        seg3 = 7'b0000001;
        seg2 = 7'b1001111;
    end
    else if(out == 4'b0010) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0010010;
    end
    else if(out == 4'b0011) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0000110;
    end
    else if(out == 4'b0100) begin
        seg3 = 7'b0000001;
        seg2 = 7'b1001100;
    end
    else if(out == 4'b0101) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0100100;
    end
    else if(out == 4'b0110) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0100000;
    end
    else if(out == 4'b0111) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0001111;
    end
    else if(out == 4'b1000) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0000000;
    end
    else if(out == 4'b1001) begin
        seg3 = 7'b0000001;
        seg2 = 7'b0000100;
    end
    else if(out == 4'b1010) begin
        seg3 = 7'b1001111;
        seg2 = 7'b0000001;
    end
    else if(out == 4'b1011) begin
        seg3 = 7'b1001111;
        seg2 = 7'b1001111;
    end
    else if(out == 4'b1100) begin
        seg3 = 7'b1001111;
        seg2 = 7'b0010010;
    end
    else if(out == 4'b1101) begin
        seg3 = 7'b1001111;
        seg2 = 7'b0000110;
    end
    else if(out == 4'b1110) begin
        seg3 = 7'b1001111;
        seg2 = 7'b1001100;
    end
    else if(out == 4'b1111) begin
        seg3 = 7'b1001111;
        seg2 = 7'b0100100;
    end
    else begin
        seg3 = 7'b1111111;
        seg2 = 7'b1111111;
    end
    
    if(direction == 1'b1) begin
        seg1 = 7'b0011101;
        seg0 = 7'b0011101;
    end
    else if(direction == 1'b0) begin
        seg1 = 7'b1100011;
        seg0 = 7'b1100011;
    end
    else begin
        seg1 = 7'b1111111;
        seg0 = 7'b1111111;
    end
end

endmodule


module debounce (pb_debounced, pb, clk);
output pb_debounced;
input pb;
input clk;

reg [3:0] DFF;

always @(posedge clk) begin
    DFF[3:1] <= DFF[2:0];
    DFF[0] <= pb;
end

assign pb_debounced = ((DFF == 4'b1111) ? 1'b1 : 1'b0);

endmodule


module onepulse (pb_debounced, clk, pb_one_pulse);
input pb_debounced;
input clk;
output reg pb_one_pulse;
reg pb_debounced_delay;

always @(posedge clk) begin
    pb_one_pulse <= pb_debounced & (! pb_debounced_delay);
    pb_debounced_delay <= pb_debounced;
end

endmodule


module ClockDivider (
    input wire clk,  // Input clock
    output reg clk_out  // Output clock
);

reg [16:0] counter;  // 17-bit counter

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == 17'd131071) begin
        clk_out <= ~clk_out;  // Toggle output clock
        counter <= 0;  // Reset counter
    end
end

endmodule


module AN_mux (
    input clk,
    input [6:0] seg3,
    input [6:0] seg2,
    input [6:0] seg1,
    input [6:0] seg0,
    output reg [6:0] seg,
    output reg [3:0] AN  // Output
);
reg [1:0] sel;
wire clk_div;
ClockDivider C1 (clk, clk_div);

always @(posedge clk_div) begin
    if(sel == 2'b11) sel <= 2'b00;
    else sel <= sel + 1'b1;
end

always @(*) begin
    if(sel == 2'b00) begin
        AN = 4'b0111;
        seg = seg3;
    end
    else if(sel == 2'b01) begin
        AN = 4'b1011;
        seg = seg2;
    end
    else if(sel == 2'b10) begin
        AN = 4'b1101;
        seg = seg1;
    end
    else if(sel == 2'b11) begin
        AN = 4'b1110;
        seg = seg0;
    end
    else begin
        AN = 4'b1111;
        seg = 7'b1111111;
    end
end

endmodule