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verilog
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module comb_shift #(parameter W=32)
(
	input [W-1:0] data_in,
	input [4:0] shamt,
	input [1:0] control,
	
	output reg [W-1:0] data_out
);
	
	
	always @(*) begin
		case(control)
			2'b00: data_out = data_in << shamt;									//LSL
			2'b01: data_out = data_in >> shamt;									//LSR
			2'b10: data_out = ($signed(data_in) >>> shamt);					//ASR: Filling the leftmost bits with the sign bit of the input data
											
			2'b11: 
					case (shamt % W)													//RR: Concatenation Operator is used
					//Modulo operator is used in case of shamt is larger than the width (W) of data_in
						5'b00000: data_out = data_in;											//shamt = 0, no shift
						5'b00001: data_out = {data_in[0], data_in[W-1:1]};
						5'b00010: data_out = {data_in[1:0], data_in[W-1:2]};
						5'b00011: data_out = {data_in[2:0], data_in[W-1:3]};
						5'b00100: data_out = {data_in[3:0], data_in[W-1:4]};
						5'b00101: data_out = {data_in[4:0], data_in[W-1:5]};
						5'b00110: data_out = {data_in[5:0], data_in[W-1:6]};
						5'b00111: data_out = {data_in[6:0], data_in[W-1:7]};
						5'b01000: data_out = {data_in[7:0], data_in[W-1:8]};
						5'b01001: data_out = {data_in[8:0], data_in[W-1:9]};
						5'b01010: data_out = {data_in[9:0], data_in[W-1:10]};
						5'b01011: data_out = {data_in[10:0], data_in[W-1:11]};
						5'b01100: data_out = {data_in[11:0], data_in[W-1:12]};
						5'b01101: data_out = {data_in[12:0], data_in[W-1:13]};
						5'b01110: data_out = {data_in[13:0], data_in[W-1:14]};
						5'b01111: data_out = {data_in[14:0], data_in[W-1:15]};		//shamt = 15
						5'b10000: data_out = {data_in[15:0], data_in[W-1:16]};
						5'b10001: data_out = {data_in[16:0], data_in[W-1:17]};
						5'b10010: data_out = {data_in[17:0], data_in[W-1:18]};
						5'b10011: data_out = {data_in[18:0], data_in[W-1:19]};
						5'b10100: data_out = {data_in[19:0], data_in[W-1:20]};
						5'b10101: data_out = {data_in[20:0], data_in[W-1:21]};
						5'b10110: data_out = {data_in[21:0], data_in[W-1:22]};
						5'b10111: data_out = {data_in[22:0], data_in[W-1:23]};
						5'b11000: data_out = {data_in[23:0], data_in[W-1:24]};
						5'b11001: data_out = {data_in[24:0], data_in[W-1:25]};
						5'b11010: data_out = {data_in[25:0], data_in[W-1:26]};
						5'b11011: data_out = {data_in[26:0], data_in[W-1:27]};
						5'b11100: data_out = {data_in[27:0], data_in[W-1:28]};
						5'b11101: data_out = {data_in[28:0], data_in[W-1:29]};
						5'b11110: data_out = {data_in[29:0], data_in[W-1:30]};
						5'b11111: data_out = {data_in[30:0], data_in[W-1:31]};		//shamt = 31
					endcase 

		endcase
		
	end
	
endmodule