Untitled

`timescale 1ns / 1ps

module LabL6;
    // Declare inputs as reg and outputs as wire
    reg [31:0] a, b;
    reg cin;
    wire [31:0] z;
    wire cout;

    // Instantiate the 32-bit adder
    yAdder my_adder(z, cout, a, b, cin);

    // Testbench variables
    reg [31:0] expected;
    reg ok;
    integer i;

    // Random seed for reproducibility
    initial begin
        $random(seed);
    end

    // Test the adder
    initial begin
        // Initialize random seed
        $random(seed);

        // Display header
        $display("a                b                | Expected z                        | Actual z          Result");
        $display("------------------------------------------------------------|--------------------------|--------");

        // Exhaustive testing for random values
        for (i = 0; i < 100; i = i + 1) begin
            // Generate random values for a and b
            a = $random;
            b = $random;
            cin = 0; // cin is fixed at 0

            // Compute the expected result
            expected = a + b;

            // Wait for 10 time units
            #10;

            // Check if the output matches the expected value
            if (expected !== z) begin
                ok = 0;
                $display("%h %h | %h          | %h   FAIL", a, b, expected, z);
            end else begin
                ok = 1;
                $display("%h %h | %h          | %h   PASS", a, b, expected, z);
            end
        end

        // Display summary
        $finish;
    end
endmodule