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// mealy_101_sequence detector-class
module mealy_101(output reg out,input x,input clk, input rst_n);
parameter [1:0] reset=2'b00, got1=2'b01,got10=2'b10,got101=2'b11;
reg [1:0] state,next;
//sequential always block
always @(posedge clk ,posedge rst_n)
begin
if(rst_n==1) state <= reset;
else state <= next;
end
// combinational always block
always@(state or x)
begin
case(state)
reset:
begin
if(x==1'b1) 
begin
out=1'b0;
next =got1;
end
else
begin
out=1'b0;		
next =reset;
end
end

got1:
begin
	if(x==1'b0)
	begin
	out=1'b0; 
	next =got10;
	end
		else
begin
		out=1'b0;
		next =got1;
		end
end
got10:
begin
	if(x==1'b1) 
	begin
	out=1'b0;
	next =got101;
	end
	else 
	begin
	out=1'b0;
	next =reset;
	end
end
got101:
begin
	if(x==1'b1) begin
	out = 1'b1;
	next =got1;
	end
		else 
		begin
		out=1'b0;
		next =got10;
		end
end
default:
begin
next =reset;
end
endcase
end
endmodule