counter and bin multiplier

Aim

Simulation of 4-bit synchronous up or down counter using Verilog.

Software used
Modelsim

Procedure
•	Type the program for the synchronous counter.
•	Compile the program.
•	Using the testbench obtain the waveform for the counter



Verilog code

module counter(clk, reset, upordown, count);
input clk, reset, upordown;
output [3:0] count;
reg [3:0] count=0;
	always@(posedge (clk) or posedge(reset))
	begin
	if(reset==1)
		count<=0;
	else
		if(upordown==1)
			if(count==15)
				count<=0;
			else
				count<=count+1;
		else
			if(count==0)
				count<=15;
			else
				count<=count-1;
	end
	endmodule
Result
Simulated 4-bit synchronous up or down counter using Verilog.


Aim
Simulate 2x2 Binary Multiplier using Verilog.

Software used
Modelsim

Procedure
•	Type the code for the binary multiplier.
•	Compile the program.
•	Type the test bench for the required program and compile.
•	Begin the simulation and check the output values in the waveform.

Observation

Verilog code

	module Mul(a,b,pro);
	input [1:0] a,b;
	output reg[3:0] pro;
	always @(a or b)
	begin 
	pro=a*b;
	end
	endmodule

Testbench

	module  testmul;
	reg[1:0] a,b;
	wire[3:0] pro;
	integer i;
	Mul uut(.a(a), .b(b), .pro(pro));
	initial begin
		a=0;
		b=0;
	end
	initial
	$ monitor(“a(%b)*b(%b)=pro(%b)”,a,b,pro);
	always @(a or b)
	begin
		for(i=0; i<4*4; i=i+1)
			#1{a,b}=i;
	# 10 $ stop;
	end
	endmodule 

Result
Simulated binary multiplier using Verilog.