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-- Library declaration
library ieee;
use ieee.std_logic_1164.all;

-- Entity declaration for sequence generator
entity Sequence_generator_stru_dataflow is
    port (
        reset, clock: in std_logic;
        y: out std_logic
    );
end entity Sequence_generator_stru_dataflow;

-- Architecture for sequence generator using structural dataflow
architecture struct of Sequence_generator_stru_dataflow is
    -- Internal signals to represent flip-flop inputs and outputs
    signal D : std_logic_vector(2 downto 0); -- 3 flip-flops needed for the states
    signal Q : std_logic_vector(2 downto 0); -- Flip-flop outputs representing state
begin

    -- Flip-flop instantiation for state transitions using D flip-flops
    -- D Flip-Flop with asynchronous reset
    process (reset, clock)
    begin
        if reset = '1' then
            Q <= "101";  -- Set the initial state when reset is high (sequence starts at 1)
        elsif rising_edge(clock) then
            Q <= D;      -- Assign next state to Q on clock's rising edge
        end if;
    end process;

    -- Next state logic based on current state (Q)
    -- Define transitions for generating the sequence 1010101
    D(2) <= Q(1);  -- Transition for the highest bit
    D(1) <= Q(0);  -- Transition for the middle bit
    D(0) <= not Q(2);  -- Transition for the lowest bit (complement of the highest bit)

    -- Output logic: The LSB of the state (Q) represents the output sequence
    y <= Q(2);

end architecture struct;