tralala

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity XorTreeStage is
	generic (N : natural);
	port(	I: in std_logic_vector(N - 1 downto 0);	-- vhodni vektor redukcije ima N vhodov
			O: out std_logic);	-- izhodni bit redukcije
end XorTreeStage;

library unisim;
use unisim.vcomponents.all;

architecture tree_of_xor_lut6 of XorTreeStage is

component XorTreeStage
	generic (N : natural);
	port(	I: in std_logic_vector(N - 1 downto 0);	-- vhodni vektor redukcije ima N vhodov
			O: out std_logic);	-- izhodni bit redukcije
end component;

begin
Stage_xor_1:
	if I'length = 1 generate		
		O <= I(0);	--xor enega bita je kar ta bit (x xor 0) = x
	end generate;
	
Stage_xor_2:
	if I'length = 2 generate
		begin
		O <= I(I'right) xor I(I'left);	-- xor dvobitnega vektorja std_logic_vector: desni bit xor levi bit
	end generate Stage_xor_2;


Stage_xor_3:
	if I'length = 3 generate
		begin

	end generate Stage_xor_3;
	
Stage_xor_4:
	if I'length = 4 generate
		begin

	end generate Stage_xor_4;
	
Stage_xor_5:
	if I'length = 5 generate
		begin

	end generate Stage_xor_5;
	
Stage_xor_6:
	if I'length = 6 generate
		begin

	end generate Stage_xor_6;
	
Stages: if I'length > 6 generate
	
	signal Sixth1_Xor, Sixth2_Xor, Sixth3_Xor, Sixth4_Xor, Sixth5_Xor, Sixth6_Xor: std_logic;
	signal Sixth1_in : std_logic_vector(I'length/6 - 1 downto 0);
	signal Sixth2_in : std_logic_vector((I'length/6)*2 - 1 downto I'length/6);
	signal Sixth3_in : std_logic_vector((I'length/6)*3 - 1 downto I'length/6*2);
	signal Sixth4_in : std_logic_vector((I'length/6)*4 - 1 downto I'length/6*3);
	signal Sixth5_in : std_logic_vector((I'length/6)*5 - 1 downto I'length/6*4);
	signal Sixth6_in : std_logic_vector(I'length - 1 downto I'length/6*5);
	
		-- razdelimo vhodni vektor na sestinah
		Sixth1_in <= I(I'length/6 - 1 downto 0);
		Sixth2_in <= I(I'length/6)*2 - 1 downto I'length/6);
		Sixth3_in <= I(I'length/6)*3 - 1 downto I'length/6*2);
		Sixth4_in <= I(I'length/6)*4 - 1 downto I'length/6*3);
		Sixth5_in <= I(I'length/6)*5 - 1 downto I'length/6*4);
		-- pri lihih vrednostih dolžine dodatni element pripišemo zg. sestini
		Sixth6_in <= I(I'length - 1 downto I'length/6*5);
				
		-- povežemo sestine
		XorTreeStage generic map (Sixth1_in'length) port map (Sixth1_in, Sixth1_Xor);
		XorTreeStage generic map (Sixth2_in'length) port map (Sixth2_in, Sixth2_Xor);
		XorTreeStage generic map (Sixth3_in'length) port map (Sixth3_in, Sixth3_Xor);
		XorTreeStage generic map (Sixth4_in'length) port map (Sixth4_in, Sixth4_Xor);
		XorTreeStage generic map (Sixth5_in'length) port map (Sixth5_in, Sixth5_Xor);
		XorTreeStage generic map (Sixth6_in'length) port map (Sixth6_in, Sixth6_Xor);
		
		-- sestine združimo z 6-vhodnimi xor vrati
		O <= Sixth1_Xor xor Sixth2_Xor xor ...; --realiziraj z lutom

	end generate Stages;
end tree_of_xor_lut6;