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`timescale 1ns / 1ps

module DataCache_tb;

    // Inputs
    reg clk;
    reg update;
    reg fill;
    reg [1:0] offset;
    reg [4:0] index;
    reg [31:0] data_in;
    reg [127:0] MsData_out;

    // Outputs
    wire [31:0] data_out;

    // Instantiate the Unit Under Test (UUT)
    DataCache uut (
        .clk(clk),
        .update(update),
        .fill(fill),
        .offset(offset),
        .index(index),
        .data_in(data_in),
        .data_out(data_out),
        .MsData_out(MsData_out)
    );

    // Clock generation
    initial begin
        clk = 0;
        forever #5 clk = !clk; // Clock with a period of 10 ns
    end

    // Stimulus here
    initial begin
        // Initialize Inputs
        update = 0;
        fill = 0;
        offset = 0;
        index = 0;
        data_in = 0;
        MsData_out = 128'hA5A5_A5A5_A5A5_A5A5_A5A5_A5A5_A5A5_A5A5;

        // Wait for global reset
        #100;

        // Fill the cache
        fill = 1; // Enable fill signal
        index = 5; // Specify the cache line to fill
        #10; // Wait a cycle
        fill = 0; // Disable fill signal

        // Update a word in the cache
        update = 1; // Enable update signal
        index = 5; // Specify the cache line to update
        offset = 2; // Specify the word to update
        data_in = 32'hDEAD_BEEF; // Data to write
        #10; // Wait a cycle
        update = 0; // Disable update signal

        // Check output
        index = 5;
        offset = 2;
        #10; // Wait a cycle to observe the data_out

        // Finish simulation
        #50;
        $finish;
    end

endmodule
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