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verilog
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module mem_addr_gen1(
    input clk,
    input rst,
    input en,
    input dir,
    input vmir,
    input hmir,
    input [9:0] h_cnt,
    input [9:0] v_cnt,
    output  wire [16:0] pixel_addr
    );
    
    wire limited_dir;
    assign limited_dir = (vmir == 1|| hmir == 1)?limited_dir:dir;
    reg [7:0] position;
    reg [16:0] tmp_adr;
    always @(*) begin
        if(en == 1)begin
            if(dir == 0)begin
                if(vmir == 0 && hmir == 0)begin
                    tmp_adr = ((h_cnt>>1)+320*(v_cnt>>1)+ position*320 )% 76800;
                end
                else if(vmir == 1 && hmir == 0)begin
                    tmp_adr = ((h_cnt>>1)+320*(239 - v_cnt>>1)+ position*320 )% 76800;
                end
                else if(vmir == 0 && hmir == 1)begin
                    tmp_adr = (319 - (h_cnt>>1)+320*(239 - v_cnt>>1)+ position*320 )% 76800;
                end
                else begin
                    tmp_adr = (319 - (h_cnt>>1)+320*(239 - v_cnt>>1)+ position*320 )% 76800;
                end
            end
            else begin
                if(vmir == 0 && hmir == 0)begin
                    tmp_adr = (v_cnt>>1 >= position) ? ((h_cnt>>1)+320*(v_cnt>>1) - position*320)% 76800 : ((h_cnt>>1)+320*(v_cnt>>1) + ( 240 - (position - v_cnt>>1))*320)% 76800;
                end
                else if(vmir == 1 && hmir == 0)begin
                    tmp_adr = (v_cnt>>1 >= position) ? ((h_cnt>>1)+320*(239- v_cnt>>1) - position*320)% 76800 : ((h_cnt>>1)+320*(239 - v_cnt>>1) + ( 240 - (position - v_cnt>>1))*320)% 76800;    
                end
                else if(vmir == 0 && hmir == 1)begin
                    tmp_adr = (v_cnt>>1 >= position) ? (319 - (h_cnt>>1)+320*(v_cnt>>1) - position*320)% 76800 : (319 - (h_cnt>>1)+320*(v_cnt>>1) + ( 240 - (position - v_cnt>>1))*320)% 76800;    
                end
                else begin
                    tmp_adr = (v_cnt>>1 >= position) ? (319 - (h_cnt>>1)+320*(239 - v_cnt>>1) - position*320)% 76800 : (319 - (h_cnt>>1)+320*(239 - v_cnt>>1) + ( 240 - (position - v_cnt>>1))*320)% 76800;
                end
            end
        end
        else begin
            tmp_adr = tmp_adr; 
        end
    end
    
    assign pixel_addr = tmp_adr;  //640*480 --> 320*240 

    always @ (posedge clk) begin
        if(rst)
            position <= 0;
        else if(position < 239)
            position <= position + 1;
            
        else if(limited_dir == 0 && position < 239)
            position <= position + 1;
        else if(limited_dir == 1 && position > 0)
            position <= position - 1;
        else
            position <= 0;
    end
    
endmodule
module lab7_1(
    input clk,
    input rst,
    input en,
    input dir,
    input vmir,
    input hmir,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,
    output hsync,
    output vsync
);
    // add your design here
    wire [11:0] data;
    wire clk_25MHz;
    wire clk_22;
    wire [16:0] pixel_addr;
    wire [11:0] pixel;
    wire valid;
    wire [9:0] h_cnt; //640
    wire [9:0] v_cnt;  //480

    assign {vgaRed, vgaGreen, vgaBlue} = pixel;

     clock_divider clk_wiz_0_inst(
      .clk(clk),
      .clk1(clk_25MHz),
      .clk22(clk_22)
    );

    mem_addr_gen1 mem_addr_gen_inst(
    .clk(clk_22),
    .rst(rst),
    .en(en),
    .dir(dir),
    .vmir(vmir),
    .hmir(hmir),
    .h_cnt(h_cnt),
    .v_cnt(v_cnt),
    .pixel_addr(pixel_addr)
    );
     
 
    blk_mem_gen_0 blk_mem_gen_0_inst(
      .clka(clk_25MHz),
      .wea(0),
      .addra(pixel_addr),
      .dina(data[11:0]),
      .douta(pixel)
    ); 

    vga_controller   vga_inst(
      .pclk(clk_25MHz),
      .reset(rst),
      .hsync(hsync),
      .vsync(vsync),
      .valid(valid),
      .h_cnt(h_cnt),
      .v_cnt(v_cnt)
    );
endmodule