Untitled

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mnoz is
	port(	   
		clk : in STD_LOGIC;
		 reset : in STD_LOGIC;
		 x1 : out STD_LOGIC;
		 x2 : out STD_LOGIC;
		 x : in STD_LOGIC_VECTOR(3 downto 0);
		 y : in STD_LOGIC_VECTOR(3 downto 0);
		 z : out STD_LOGIC_VECTOR(7 downto 0)
	     );
end mnoz;

architecture mnoz_a of mnoz is	  
signal new_rg1,rg1:std_logic_vector(4 downto 0);	
signal rg2,rg3,rg4:std_logic_vector(3 downto 0); 
signal d :std_logic;

begin
 new_rg1<=('0' & rg3)+('0' & rg1(3 downto 0));
 process(clk,reset)
 variable rg3z : std_logic_vector(3 downto 0);
 begin
	 if reset='1' then
		 rg3z:=(others=>'0');
	elsif clk'event and clk='1' then
		if y1='1' then 
			rg3z:=x;
		end if;
		rg3<=rg3z;
	end process;
	
	process(clk reset)
	variable rg1z:std_logic_vector(4 downto 0);
	variable zm:std_logic_vector(2 downto 0);
	begin	
		if reset='1' then
			rg1z:=(others='1');
		elsif clk'event and clk='1' then	
			zm:= y1 & y2 & y3;
		case zm is 
			when "100" =>
			rg1z:=(others=>'0');
			when "010" =>
			rg1z:=new_rg1;
			when "001" =>
			rg1z:='0' & rg1z(4 downto 1);
			when orhers =>
			
		end case;
		end if;
		rf1<=rg1z;
		end process;
		
		process(clk,reset)
		variable rg2z : std_logic_vector(3 downto 0);
		variable zm : std_logic_vector(2 downto 0);
		begin
			if reset='1' then 
				rg2z:=(other=>'0');
			elsif clk'event and clk='1' then
				zm:=y1 & y2 & y3;
	case zm is
		when "100" =>
		rg2z:=y;	 
		when "001" =>
			rg2z:=rg1(0) & rg2z(3 downto 1);
		when OTHERS =>
	end case;	
	end if;
	rg2<=rg2z;
	end process;
	process(clk,reset)
	variable d : std_logic;
	variable zm : std_logic_vector(2 downto 0);
	begin
	if reset='1' then
		d:='0';
	elsif clk'event and clk='1' then
		zm:=y1 & y2 & y3 ;
		case zm is 
			when "100" =>
			d:='0';
			when "001" =>
			d:=rg2(0);
			when OTHers =>
		end case;
	end if;
	x1<=d;
	end process;
	
	process(clk,reset)
	variable rg4z : std_logic_vector(3 downto 0);
	variable zm : std_logic_vector(2 downto 0);
	begin
		if reset='1' then
			rg4z:=(others=>'0');
		elsif clk'event and clk='1' then
			zm:= y1 & y2 & y3;
		case zm is
			when "100" =>
			rg4z:= "0101";
			when "001" =>
			rg4z:=rg4z-1;
			when others =>
			
	end case;
	end if;
	rg4<rg4z;
	end process;
	x2<='1' when rg4=0 else '0';
		z<= rg1(3 downto 0) & rg2(3 downto 0);
		

end mnoz_a;