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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity parallel_adder is
port( A,B: in STD_LOGIC_VECTOR(3 downto 0);
S: out STD_LOGIC_VECTOR(3 downto 0);
Cin: in STD_LOGIC;
Cout: out STD_LOGIC
);
end parallel_adder;
architecture Behavioral of parallel_adder is
begin
process (A,B,Cin)
variable t: STD_LOGIC;
begin
t :=Cin;
for i in 0 to 3 loop
S(i)<=A(i) Xor B(i) Xor t;
t := (A(i) and B(i)) or (t and A(i) or (t and B(i)));

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end loop;
Cout<=t;
end process;
end Behavioral;