Untitled

 `timescale 1ns / 1ps
 module LCD_FSM(
 output reg [7:0] LCD_DATA,
 output reg LCD_ENABLE,
 output reg LCD_RS,
 input CLK,
 input RST
 );
 // State Definitions
 parameter S0 = 5'd0, S1 = 5'd1, S2 = 5'd2, S3 = 5'd3, S4 = 5'd4,
 S5 =5'd5, S6 = 5'd6, S7 = 5'd7, S8 = 5'd8, S9 = 5'd9,
 S10 = 5'd10, S11 = 5'd11, S12 = 5'd12, S13 = 5'd13, S14 = 5'd14,
 S15 = 5'd15, S16 = 5'd16, S17 = 5'd17, S18 = 5'd18, S19 = 5'd19,
 S20 = 5'd20, S21 = 5'd21, S22 = 5'd22, S23 = 5'd23, S24 = 5'd24,
 S25 = 5'd25, S26 = 5'd26, S27 = 5'd27, IDLE = 5'd28;
 reg [4:0] current_state;
 integer cnt;
 always @(posedge CLK or posedge RST) begin
if (RST) begin
 cnt <= 0;
 current_state <= S0;
 LCD_DATA <= 8'b00000000;
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end else begin
 // Adjusting the timing to ensure proper state transitions
 if (cnt < 10) begin
 cnt <= cnt + 1; // Reduced timing for quicker state changes
 end else begin
 cnt <= 0; // Reset the counter
 case (current_state)
 S0: begin
 current_state <= S1;
 LCD_DATA <= 8'h38; // Function Set: 8-bit mode
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end
 S1: begin
 current_state <= S2;
 LCD_DATA <= 8'h38;
 LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b0;
 end
 S2: begin
 current_state <= S3;
 LCD_DATA <= 8'h38;
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end
 S3: begin
 current_state <= S4;
 LCD_DATA <= 8'b00000001; // Clear Display
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end
 S4: begin
 current_state <= S5;
 LCD_DATA <= 8'b00000001;
 LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b0;
 end
 S5: begin
 current_state <= S6;
 LCD_DATA <= 8'b00000001;
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end
 S6: begin
current_state <= S7;
 LCD_DATA <= 8'b00001110; // Display On, Cursor On, Blink On
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end
 S7: begin
 current_state <= S8;
 LCD_DATA <= 8'b00001110;
 LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b0;
 end
 S8: begin
 current_state <= S9;
 LCD_DATA <= 8'b00001110;
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b1;
 end
 S9: begin
 current_state <= S10;
 LCD_DATA <= 8'h4E; // N
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b1;
 end
 S10: begin
 current_state <= S11;
 LCD_DATA <= 8'h55; // U
 LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b1;
 end
 S11: begin
 current_state <= S12;
 LCD_DATA <= 8'h55; // U
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b1;
 end
 S12: begin
 current_state <= S13;
 LCD_DATA <= 8'h54; // T
 LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b1;
 end
 S13: begin
 current_state <= S14;
 LCD_DATA <= 8'h54; // T
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b1;
 end
 S14: begin
 current_state <= S15;
 LCD_DATA <= 8'h45; // E
LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b1;
 end
 S15: begin
 current_state <= S16;
 LCD_DATA <= 8'h45; // E
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b1;
 end
 S16: begin
 current_state <= S17;
 LCD_DATA <= 8'h43; // C
 LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b1;
 end
 S17: begin
 current_state <= S18;
 LCD_DATA <= 8'h48; // H
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b1;
 end
 S18: begin
 current_state <= S19;
 LCD_DATA <= 8'h00; // Null Character to end
 LCD_ENABLE <= 1'b1;
 LCD_RS <= 1'b1;
 end
 S19: begin
 current_state <= S20;
 LCD_DATA <= 8'h00; // Null Character to end
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end
 default: begin
 current_state <= IDLE;
 LCD_DATA <= 8'b00000000;
 LCD_ENABLE <= 1'b0;
 LCD_RS <= 1'b0;
 end
 endcase
 end
 end
 end
 endmodule