Untitled

1-1
module test(a,b,sum,carry);

input a,b;
output sum, carry;

xor(sum,a,b);
and(carry,a,b);

endmodule

1-2
module test(a,b,sum, carry);

input a,b;
output sum, carry;


assign sum = (a^b);
assign carry = (a&b);

endmodule

1-3
module test(a,b,sum, carry);

input a,b;
output sum, carry;
reg sum, carry;

always @(a,b)
begin
	sum = (a^b);
	carry = (a&b);
end

endmodule

2-1
module test(a,b,c,sum, carry);

input a,b,c;
output sum, carry;
wire [2:0] temp;

xor(temp[0],a,b);
xor(sum,temp[0],c);
and(temp[1],temp[0],c);
and(temp[2],a,b);
or(carry,temp[1],temp[2]);

endmodule

2-2
module test(a,b,c,sum, carry);

input a,b,c;
output sum, carry;

assign sum = ((a^b)^c);
assign carry = ((a^b)&c)|(a&b);

endmodule

2-3
module test(a,b,c,sum, carry);

input a,b,c;
output sum, carry;
reg sum, carry;

always @(a,b,c)
begin
	sum = ((a^b)^c);
	carry = ((a^b)&c)|(a&b);
end

endmodule