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module pipelined_carry_lookahead_adder #(parameter WIDTH = 4) ( input clk, input [WIDTH-1:0] i_add1, input [WIDTH-1:0] i_add2, output [WIDTH:0] o_result ); wire [WIDTH:0] w_C; wire [WIDTH-1:0] w_G, w_P, w_SUM; wire [WIDTH-1:0] w_SUM_stage1, w_SUM_stage2; wire [WIDTH:0] w_C_stage2; // Stage 1: Full Adders genvar ii; generate for (ii = 0; ii < WIDTH; ii = ii + 1) begin assign w_SUM[ii] = i_add1[ii] ^ i_add2[ii] ^ w_C[ii]; end endgenerate N_bit_register #(WIDTH) reg_stage1 (.clk(clk), .d(w_SUM), .q(w_SUM_stage1)); // Stage 2: Generate and Propagate Terms genvar jj; generate for (jj = 0; jj < WIDTH; jj = jj + 1) begin assign w_G[jj] = i_add1[jj] & i_add2[jj]; assign w_P[jj] = i_add1[jj] | i_add2[jj]; end endgenerate // Stage 3: Carry Terms generate for (jj = 0; jj < WIDTH; jj = jj + 1) begin assign w_C[jj + 1] = w_G[jj] | (w_P[jj] & w_C[jj]); end endgenerate N_bit_register #(WIDTH) reg_stage2 (.clk(clk), .d(w_C[WIDTH-1:0]), .q(w_C_stage2)); N_bit_register #(WIDTH) reg_stage3 (.clk(clk), .d(w_SUM_stage1), .q(w_SUM_stage2)); assign w_C[0] = 1'b0; // no carry input on first adder assign o_result = {w_C_stage2[WIDTH], w_SUM_stage2}; // Verilog Concatenation endmodule
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