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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_Shifter is
end tb_Shifter;

architecture Behavioral of tb_Shifter is
    -- Component Declaration
    component Shifter
        port(
            shift_lsl  : in  std_logic;
            shift_lsr  : in  std_logic;
            shift_asr  : in  std_logic;
            shift_ror  : in  std_logic;
            shift_rrx  : in  std_logic;
            shift_val  : in  std_logic_vector(4 downto 0);
            din        : in  std_logic_vector(31 downto 0);
            cin        : in  std_logic;
            dout       : out std_logic_vector(31 downto 0);
            cout       : out std_logic;
            vdd        : in  bit;
            vss        : in  bit
        );
    end component;

    -- Test signals
    signal shift_lsl  : std_logic := '0';
    signal shift_lsr  : std_logic := '0';
    signal shift_asr  : std_logic := '0';
    signal shift_ror  : std_logic := '0';
    signal shift_rrx  : std_logic := '0';
    signal shift_val  : std_logic_vector(4 downto 0) := "00000";
    signal din        : std_logic_vector(31 downto 0) := (others => '0');
    signal cin        : std_logic := '0';
    signal dout       : std_logic_vector(31 downto 0);
    signal cout       : std_logic;

begin
    -- Instantiate the Unit Under Test (UUT)
    uut: Shifter
        port map(
            shift_lsl  => shift_lsl,
            shift_lsr  => shift_lsr,
            shift_asr  => shift_asr,
            shift_ror  => shift_ror,
            shift_rrx  => shift_rrx,
            shift_val  => shift_val,
            din        => din,
            cin        => cin,
            dout       => dout,
            cout       => cout,
            vdd        => '1',
            vss        => '0'
        );

    -- Stimulus process
    stimulus: process
    begin
        -- Test LSL
        din <= x"00010000";
        shift_lsl <= '1';
        shift_val <= "00001"; -- Shift left by 1
        wait for 5 ns;
        shift_lsl <= '0';
        
        -- Test LSR
        shift_lsr <= '1';
        shift_val <= "00001"; -- Shift right by 1
        wait for 5 ns;
        shift_lsr <= '0';

        -- Test ASR
        din <= x"80000001"; -- Sign bit set
        shift_asr <= '1';
        shift_val <= "00001"; -- Arithmetic shift right by 1
        wait for 5 ns;
        shift_asr <= '0';

        -- Test ROR
        din <= x"00000001";
        shift_ror <= '1';
        shift_val <= "00001"; -- Rotate right by 1
        wait for 5 ns;
        shift_ror <= '0';

        -- Test RRX
        din <= x"00000001";
        cin <= '1';
        shift_rrx <= '1'; -- Rotate right with carry
        wait for 5 ns;
        shift_rrx <= '0';

        wait;
    end process;
end Behavioral;