Untitled

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is 
port(  Clk : in std_logic; --clock signal
	A,B : in signed (7 downto 0); --input operands
	Sel : in unsigned(2 downto 0); --Operation to be
	R  : out signed (7 downto 0); --output of ALU
	);
end ALU; 

architecture Behavioral of ALU is 

--temporary signal declaration.
signal R1, R2, R3 : signed(7 downto 0) := (others => '0')

begin 
	R1 <= A;
	R2 <= B;
	R <= R3;
process(Clk)
begin

if(rising_edge(Clk)) then
	case Sel is 
		when "000" =>
			R3 <= R1 + R2;
		when "001" =>
			R3 = R1 - R2;
		when "010" =>
			R3 = not R1;
		when "011" =>
			R3 = R1 nand R2;
		when "100" =>
			R3 = R1 xor R2;
		when others =>
			NULL;
	end case;
end if;
end process;