library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
ENTITY UartTest IS
PORT (
VS : OUT STD_LOGIC_VECTOR(2 downto 0); VS_EN : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
led: OUT STD_LOGIC := '0';
RX : in STD_LOGIC := '1';
TX : out STD_LOGIC := '1'
);
END UartTest;
ARCHITECTURE BEHAVIORAL OF UartTest IS
CONSTANT UART_Interface_D_Width : INTEGER := 8;
SIGNAL UART_Interface_Reset : STD_LOGIC := '0';
SIGNAL UART_Interface_TX_Enable : STD_LOGIC := '0';
SIGNAL UART_Interface_TX_Busy : STD_LOGIC := '0';
SIGNAL UART_Interface_TX_Data : STD_LOGIC_VECTOR(UART_Interface_D_Width - 1 downto 0) := (others => '0');
SIGNAL UART_Interface_RX_Busy : STD_LOGIC := '0';
SIGNAL UART_Interface_RX_Data : STD_LOGIC_VECTOR(UART_Interface_D_Width - 1 downto 0) := (others => '0');
SIGNAL UART_Interface_RX_Error : STD_LOGIC := '0';
COMPONENT UART_Interface IS
GENERIC (
CLK_Frequency : INTEGER := 12000000;
Baud_Rate : INTEGER := 19200;
OS_Rate : INTEGER := 16;
D_Width : INTEGER := 8;
Parity : INTEGER := 0;
Parity_EO : STD_LOGIC := '0'
);
PORT (
CLK : IN STD_LOGIC;
Reset : IN STD_LOGIC := '0';
RX : IN STD_LOGIC := '1';
TX : OUT STD_LOGIC := '1';
TX_Enable : IN STD_LOGIC := '0';
TX_Busy : OUT STD_LOGIC := '0';
TX_Data : IN STD_LOGIC_VECTOR(D_Width-1 DOWNTO 0) := (others => '0');
RX_Busy : OUT STD_LOGIC := '0';
RX_Data : OUT STD_LOGIC_VECTOR(D_Width-1 DOWNTO 0) := (others => '0');
RX_Error : OUT STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
VS <= "000"; VS_EN <= '1';
UART_Interface1 : UART_Interface
GENERIC MAP (
CLK_Frequency => 12000000,Baud_Rate => 19200,OS_Rate => 16,D_Width => UART_Interface_D_Width,Parity => 0,Parity_EO => '0'
) PORT MAP (
CLK => CLK,
Reset => UART_Interface_Reset,RX => RX,TX => TX,TX_Enable => UART_Interface_TX_Enable,TX_Busy => UART_Interface_TX_Busy,TX_Data => UART_Interface_TX_Data,RX_Busy => UART_Interface_RX_Busy,RX_Data => UART_Interface_RX_Data,RX_Error => UART_Interface_RX_Error
);
PROCESS (CLK)
VARIABLE Thread4 : NATURAL range 0 to 60000005 := 0;
BEGIN
IF RISING_EDGE(CLK) THEN
CASE (Thread4) IS
WHEN 0 =>
UART_Interface_TX_Data <= "10101010";
UART_Interface_TX_Enable <= '1';
Thread4 := 1;
WHEN 1 =>
IF (UART_Interface_RX_Busy = '0') THEN
ELSE
Thread4 := Thread4 + 1;
END IF;
WHEN 2 =>
UART_Interface_TX_Enable <= '0';
Thread4 := 3;
WHEN 3 =>
IF (UART_Interface_RX_Busy = '1') THEN
ELSE
Thread4 := Thread4 + 1;
END IF;
WHEN 4 to 60000004 =>
IF (Thread4 < 60000004) THEN
Thread4 := Thread4 + 1;
ELSE
Thread4 := 0;
END IF;
WHEN others => Thread4 := 0;
END CASE;
END IF;
END PROCESS;
END BEHAVIORAL;