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2 years ago
3.8 kB
`timescale 1ns / 1ps
`default_nettype none

module top_level( input wire clk_100mhz,
                  input wire btnd,btnc,
                  input wire ps2_clk,
                  input wire ps2_data,
                  output logic [15:0] led,
                  output logic ca, cb, cc, cd, ce, cf, cg,
                  output logic [7:0] an 

  /* have btnd control system reset */
  logic sys_rst;
  assign sys_rst = btnd;

   /* TODO: you will write this in
   * part 3 of the lab from scratch@
  logic [7:0] ps2_buffer [3:0];
  logic [7:0] ps2_code;
  logic ps2_valid;

  /* how many button presses have we seen so far?
   * wire this up to the LED display
  logic [15:0] btn_count;
  //assign led = btn_count; //uncomment to display btn_count on led
  assign led = {ps2_buffer[1], ps2_buffer[0]}; //for test bench purposes

  /* this should go high for one cycle on the
   * rising edge of the (debounced) button output
  logic btn_pulse;

  /* debouncer for the button. we wrote this
   * in lecture together.
   * TODO: make a variable for the debounced
   * button output, and feed it into your edge
   * detector
  logic btnc_out; 
  debouncer btnc_db(.clk_in(clk_100mhz),

  /* TODO: write your edge detector for part 1 of the
   * lab here!

  edge_detector edge_1 (.clk_in(clk_100mhz), 

  /* the button-press counter.
   * TODO: finish this during part 1 of the lab
  simple_counter msc( .clk_in(clk_100mhz),

  /* TODO: you'll finish this in part 2 of the lab. this will
   * render the button count and the four PS/2 buffer
   * values in parts 2 and 3 respectively

  /* For part 1 of the lab, you won't use this yet! So leave
   * this commented out unless you want errors hehe

   seven_segment_controller mssc(.clk_in(clk_100mhz),
                                  .val_in({ps2_buffer[3], ps2_buffer[2], ps2_buffer[1], ps2_buffer[0]}),
                                  .cat_out({cg, cf, ce, cd, cc, cb, ca}),

  /* Delete this once you're done with part 2 of the lab */
  // assign {cg, cf, ce, cd, cc, cb, ca} = 8'b0;
  // assign an = 8'b1111_1111;

  /* pull inputs from the ~15KHz PS/2 domain
   * our FPGA's 100 MHz clock domain. this code
   * acts as a 'synchronizer' - we will talk more
   * about this later. for now, don't change it
  logic [1:0] ps2b_c;
  logic [1:0] ps2b_d;

  always_ff @(posedge clk_100mhz)begin
    ps2b_c[0] <= ps2_clk;
    ps2b_d[0] <= ps2_data;
    ps2b_c[1] <= ps2b_c[0];
    ps2b_d[1] <= ps2b_d[0];

  always_ff @(posedge clk_100mhz) begin
    if (ps2b_c[0] == 1'b0 && ps2b_c[1] == 1'b1) begin 
      if (ps2_valid == 1'b1 || ps2_code == 8'h00) begin 
        ps2_buffer[0] <= ps2_code;
        ps2_buffer[1] <= ps2_buffer[0];
        ps2_buffer[2] <= ps2_buffer[1];
        ps2_buffer[3] <= ps2_buffer[2];
      end else begin 
    end else begin 

  /* Leave this commented out until you get to part 3
   * unless you would like to see more errors...

  ps2_decoder mpd (.clk_in(clk_100mhz),


`default_nettype none