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module alu(a, b, alucontrol, result, zero); input \( [63: 0] \) a, b; input \( [2: 0] \) alucontrol; output reg [63:0] result
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Given Design is an Arithmetic Logic Design (ALU) that can implement 8 different instructions.
Those are 
                and  -> logical and operation
                or     -> logical or operation
                add  -> addition
                sll     -> shift left logically
                srl     -> shift right logically
                sub   -> subtraction
                xor    -> logical xor operation
                slt     -> Set if less than i.e., it is 1 if a is less than 1 otherwise 0.

this ALU consists of


       -> two data inputs are a and b which are of 64 bits in width each
       -> one control input is alucontrol which is of 3 bits
       -> one output variable result which is of 64 bits
       -> one bit flag output zero to detect whether the output result is zero or not.
Explanation:

As alucontrol input is of 3 bits we can have 8 different combinations, For each one combination, we are going to implement one instruction according to the table given in the question


Block diagram for the ALU

Now we are going to implement this ALU using the Verilog Hardware Description language.

Verilog code:

module alu (a, b, alucontrol, result, zero);


//inputs
input [63:0]a, b;

input [2:0]alucontrol;


//outputsNow, we are going t

output zero;

output reg [63:0]result;


always @(*)

 begin

    case(alucontrol)

        3'b000:  result <= #20 a+b;  //add
        3'b001:  result <= #20 a-b;   //sub

        3'b010:  result <= #20 a & b;  //and

        3'b011:  result <= #20 a | b;   //or

        3'b100:  result <= #20 a^b;    //xor

        3'b101:  result <= #20  (a<b)? 64'd1:64'd0;  //slt  

        3'b110:  result <= #20 a<<1;    //sll
        3'b111:  result <= #20 a>>1;    //srl
        default: result <= 64'bx;

   endcase

 end


assign zero = (result==0)? 1 : 0;

endmodule


Explanation:

-> As we are using Non Blocking assignments we should declare the output variable result as reg

-> In the question they have given that "All operations must have a delay of 20 before the output is available" that's why we have given #20 delay before assigning the calculated value to the output variable. 


Based on the given specifications in the question for the ALU, we have implemented that ALU using Verilog Language