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`timescale 1ns / 1ps module LabL3; // Declare inputs as reg and output as wire with 32-bit width reg [31:0] a, b; reg c; wire [31:0] z; // Instantiate the 32-bit 2-to-1 multiplexer yMux #(32) my_mux(z, a, b, c); // Test the multiplexer initial begin // Display header $display("c a b | z"); $display("-------------------------------------------------|------------------------------"); // Apply different combinations of inputs and display the results a = 32'h00000000; b = 32'h00000001; c = 0; #10 $display("%b %h %h | %h", c, a, b, z); a = 32'h00000000; b = 32'h00000001; c = 1; #10 $display("%b %h %h | %h", c, a, b, z); a = 32'hAAAAAAAA; b = 32'h55555555; c = 0; #10 $display("%b %h %h | %h", c, a, b, z); a = 32'hAAAAAAAA; b = 32'h55555555; c = 1; #10 $display("%b %h %h | %h", c, a, b, z); // Finish simulation $finish; end endmodule
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