Pas de titre

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity seg is
port (CLK,RST : in std_logic;
        A: out std_logic;
        B: out std_logic;
        C: out std_logic;
        D: out std_logic;
        E: out std_logic;
        F: out std_logic;
        G: out std_logic;
        an0: out std_logic;
        an1: out std_logic;
        an2: out std_logic;
        an3: out std_logic;
        dp: out std_logic);
        
end seg;

 

architecture rtl of seg is
signal cnt : std_logic_vector(23 downto 0);
begin
    process (CLK,RST)
    begin
        if (RST = '1') then
            cnt <= (others => '0');
        elsif (CLK'event and CLK = '1') then
            cnt <= cnt +1;
        end if;
    end process;

 

A <= '0';B <= '0';C <= '0';D <= '1';E <= '1';F <= '1';G <= '1';

 

an0 <= '0';an1 <= '0';an2 <= '0';an3 <= '0';

 


end rtl;