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//******************************************************************************
// MSP430FR235x Demo - SAC-L3, DAC Buffer Mode
//
// Description: Configure SAC-L3 for DAC Buffer Mode. Use the 12 bit DAC to
// output positive ramp. The OA is set in buffer mode to improve DAC output
// drive strength. Internal 2.5V reference is selected as DAC reference.
// Observe the output of OA0O pin with oscilloscope.
// ACLK = n/a, MCLK = SMCLK = default DCODIV ~1MHz.
//
// MSP430FR235x
// -------------------
// /|\| |
// | | |
// --|RST DAC12->OA0O|--> P1.1 oscilloscope
// | |
// | |
// | |
// | |
// | |
//
// Darren Lu
// Texas Instruments Inc.
// Oct. 2016
// Built with IAR Embedded Workbench v6.50 & Code Composer Studio v6.2
//******************************************************************************
#include <msp430.h>
unsigned int DAC_data=0;
unsigned int i=0;
unsigned int sin[50]={2048,2304,2557,2801,3034,3251,3449,3625,3776,3900,
3995,4059,4091,4091,4059,3995,3900,3776,3625,3449,
3251,3034,2801,2557,2304,2048,1791,1538,1294,1061,
844,646,470,319,195,100,36,4,4,36,
100,195,319,470,646,844,1061,1294,1538,1791};
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watch dog timer
P1SEL0 |= BIT1; // Select P1.1 as OA0O function
P1SEL1 |= BIT1; // OA is used as buffer for DAC
PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
// Configure reference module
PMMCTL0_H = PMMPW_H; // Unlock the PMM registers
PMMCTL2 = INTREFEN | REFVSEL_1; // Enable internal 2V reference
while(!(PMMCTL2 & REFGENRDY)); // Poll till internal reference settles
SAC0DAC = DACSREF_1 + DACLSEL_2 + DACIE; // Select int Vref as DAC reference
SAC0DAT = sin[0]; // Initial DAC data
SAC0DAC |= DACEN; // Enable DAC
SAC0OA = NMUXEN + PMUXEN + PSEL_1 + NSEL_1;//Select positive and negative pin input
SAC0OA |= OAPM; // Select low speed and low power mode
SAC0PGA = MSEL_1; // Set OA as buffer mode
SAC0OA |= SACEN + OAEN; // Enable SAC and OA
// Use TB2.1 as DAC hardware trigger
TB2CCR0 = 80-1; // PWM Period/2
TB2CCTL1 = OUTMOD_6; // TBCCR1 toggle/set
TB2CCR1 = 40; // TBCCR1 PWM duty cycle
TB2CTL = TBSSEL__SMCLK | MC_1 | TBCLR; // SMCLK, up mode, clear TBR
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, Enable Interrupt
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = SAC0_SAC2_VECTOR
__interrupt void SAC0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(SAC0_SAC2_VECTOR))) SAC0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(SAC0IV,SACIV_4))
{
case SACIV_0: break;
case SACIV_2: break;
case SACIV_4:
//DAC_data++;
// DAC_data &= 0xFFF;
i++;
SAC0DAT = sin[i]; // DAC12 output positive ramp
if(i==49)
i=0;
break;
default: break;
}
}
Notite
Gen semnal
Sensibilitatea = Vout = (Vref/ Nrbiti) * NrDAC_DATA = 3.3/4096 * [0...4095]
T = Nep * Tgen
Tgen = 1/10Khz
Tgen = 0.1
Nep = 50 * 100qs (10kHz) = 5000 microsecunde
0,2 * 10^3 = 200Hz