Untitled
unknown
scala
a year ago
476 B
5
Indexable
import chisel3.{Bundle, Module, _} class HelloTop extends Module { val io = IO(new Bundle { val led = Output(UInt(1.W)) val seg = Output(UInt(7.W)) val an = Output(UInt(4.W)) }) val counter = Module(new SignalCounter(width = 4, max_count = 8)) counter.io.signal := true.B io.led := 1.U io.seg := 1.U io.an := counter.io.out } object HelloTop extends App { (new chisel3.stage.ChiselStage).emitVerilog(new HelloTop()) }
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