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module clock_divider(clk,clk_div);
    input clk;
    output clk_div;
    parameter n = 25;
    reg[n-1:0]num;
    wire[n-1:0]next_num;
    always@(posedge clk)begin
        num <= next_num;
    end
    assign next_num = num + 1;
    assign clk_div = num[n-1];
endmodule

module lab3_1(
    input clk,
    input rst,
    input en,
    input speed,
    output reg [15:0] led
);
// add your design here
wire clk_div25, clk_div27;
reg [1:0] state;
reg [1:0] next_state;

clock_divider #(25) div1(.clk(clk), .clk_div(clk_div25));
clock_divider #(27) div2(.clk(clk), .clk_div(clk_div27));

//change speed by switch
always @(posedge clk_div25 or posedge rst) begin
    if(rst) begin
        state <= 0;
        led <= 0;
        next_state <= 0;
    end 
    else begin
        if (en && speed == 0) begin
            case (state)
                2'b00: led <= 16'b1111111111111111;
                2'b01: led <= 16'b1000100010001000;
                2'b10: led <= 16'b1110111011101110;
                2'b11: led <= 16'b1111111111111111;
                default: led <= 16'b0000000000000000; 
            endcase
            state <= next_state;
        end
        else
            led <= led;
    end
end

always @(posedge clk_div27 or posedge rst) begin
    if(rst) begin
        state <= 0;
        led <= 0;
        next_state <= 0;
    end 
    else begin
    if (en && speed == 1) begin
        case (state)
            2'b00: led <= 16'b1111111111111111;
            2'b01: led <= 16'b1000100010001000;
            2'b10: led <= 16'b1110111011101110;
            2'b11: led <= 16'b1111111111111111;
            default: led <= 16'b0000000000000000; 
        endcase
        state <= next_state;
    end
    else 
        led <= led;
    end
end

always @(*) begin
    if(state == 2'b11)
        next_state = 0;
    else
        next_state = state + 1;
end

endmodule