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void chSwitchStaMigrationDoneCmdHandler(HOST_CMD_DESC_S *pCmdDesc)
{
  TX_MNG_STA_MIG_PARAMS_S *pMigParams = pCmdDesc->cmdBuff;
  U32 linkId = stationIdToLinkId(pMigParams->staId, FALSE);

  if (--g_chSwitchRspCntr == 0)
  {
    // itzik: check for all fifos that there is no frames on status fifo of other lmac
    U32 i;
    U32 fifoNum;

    for (fifoNum = 0; i < 32; fifoNum++;)
    {
      U32 sttsFifo = SCD_GET_STTS_FIFO_WR_RD_PTRS(fifoNum);
      U32 rdPtr = SCD_GET_STATUS_FIFO_RDPTR(sttsFifo);
      U32 wrPtr = SCD_GET_STATUS_FIFO_WRPTR(sttsFifo);

      for (i = rdPtr; i < wrPtr; i++;)
      {
        U32 entry = g_pScdMemoryTableDb->txfStatusFifo[fifoNum].entry[i];
        U32 tfdqNum = SHIFT_AND_MASK(entry, SCD_TXF_STTS_FIFO_RTDQ_NUM_MSK, SCD_TXF_STTS_FIFO_RTDQ_NUM_POS);
        U32 txfMapped = SHIFT_AND_MASK(NEVO_REG_READ(&SCD_STTS_TFDQ0[tfdqNum], SCD_STTS_TFDQ_TXF_NUM_MSK, SCD_STTS_TFDQ_TXF_NUM_POS);
        U32 txfValid = SHIFT_AND_MASK(NEVO_REG_READ(&SCD_STTS_TFDQ0[tfdqNum], SCD_STTS_TFDQ_TXF_VALID_MSK, SCD_STTS_TFDQ_TXF_VALID_POS);
        U32 sn = SHIFT_AND_MASK(entry, SCD_TXF_STTS_FIFO_SN_NUMBER_MSK, SCD_TXF_STTS_FIFO_SN_NUMBER_POS);
        U32 tfdqStatusEntry = g_pScdMemoryTableDb->tfdStatus.tfdQueue[tfdqNum][sn >> 3]; // select dword entry from 0 to 127
        U32 tfdqStatusPos = sn % 8; // byte selected index pos
        U32 tfdqStatusMsk = 0xff << tfdqStatusPos;
        U32 tfdqStatus = SHIFT_AND_MASK(tfdqStatusEntry, tfdqStatusMsk, tfdqStatusPos);
        U32 lmacId = tfdqStatus & BIT(3); // bit 3 indicate lmac index

        if (!txfValid)
        {
          continue;
        }

        if ((txfMapped < 16 && lmacId == 1) ||
            (txfMapped >= 16 && lmacId == 0))
        {
          SYSASSERT(FALSE, 0xCAFE1, fifoNum, tfdqNum, i);
        }
      }
    }

    macDomainChannelSwitchComplete(linkId);
  }
}