Untitled

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder is
  Port ( i2,i1,i0 : in  STD_LOGIC;
          d : out  STD_LOGIC_vector(7 downto 0));
         end decoder;
architecture Behavioral of decoder is
begin
process(i2,i1,i0)
variable input : std_logic_vector(2 DOWNTO 0);
     begin
       input:=i2&i1&i0;
          
      case input is
                when "000"=>d<="00000001";
                when "001"=>d<="00000010";
                when "010"=>d<="00000100";
                when "011"=>d<="00001000";
               when "100"=>d<="00010000";
               when "101"=>d<="00100000";
 when "110"=>d<="01000000";
              when others=>d<="10000000";
       end case;
end process;
end Behavioral;