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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.common_pack.all; entity cmdProc is port ( clk : in std_logic; reset : in std_logic; rxnow : in std_logic; rxData : in std_logic_vector (7 downto 0); txData : out std_logic_vector (7 downto 0); rxdone : out std_logic; ovErr : in std_logic; framErr : in std_logic; txnow : out std_logic; txdone : in std_logic; start : out std_logic; numWords_bcd : out BCD_ARRAY_TYPE(2 downto 0); byte_hex_list : inout CHAR_ARRAY_TYPE(13 downto 0); dataReady : in std_logic; byte : in std_logic_vector(7 downto 0); maxIndex : in BCD_ARRAY_TYPE(2 downto 0); dataResults : in CHAR_ARRAY_TYPE(0 to RESULT_BYTE_NUM-1); seqDone : in std_logic ); end cmdProc; architecture arch of cmdProc is function hexConvert(nibble: std_logic_vector(3 downto 0)) return std_logic_vector is begin case nibble is when "0000" => return "00110000"; -- '0' when "0001" => return "00110001"; -- '1' when "0010" => return "00110010"; -- '2' when "0011" => return "00110011"; -- '3' when "0100" => return "00110100"; -- '4' when "0101" => return "00110101"; -- '5' when "0110" => return "00110110"; -- '6' when "0111" => return "00110111"; -- '7' when "1000" => return "00111000"; -- '8' when "1001" => return "00111001"; -- '9' when "1010" => return "00111010"; -- 'A' when "1011" => return "00111011"; -- 'B' when "1100" => return "00111100"; -- 'C' when "1101" => return "00111101"; -- 'D' when "1110" => return "00111110"; -- 'E' when others => return "00111111"; -- 'F' end case; end function; type state_type is (IDLE, SEND, cmdA_proc, cmdP_proc, cmdL_proc, byteFirstHalf, byteSecondHalf, printSpaceCMDA, pPeakSecondHalf, printSpaceCMDP, cmdP_print1, cmdP_print2, cmdP_print3, l1nibble2, l1nibbleSpace, l2nibble1, l2nibble2, l2nibbleSpace, l3nibble1, l3nibble2, l3nibbleSpace, l4nibble1, l4nibble2, l4nibbleSpace, l5nibble1, l5nibble2, l5nibbleSpace, l6nibble1, l6nibble2, l6nibbleSpace, l7nibble1, l7nibble2, START_TRANSMIT, TRANSMIT_DATA, numWords1, numWords2, numWords3, IDLE1, START_TRANSMIT1, TRANSMIT_DATA1, IDLE2, START_TRANSMIT2, TRANSMIT_DATA2); signal curState, nextState : state_type; signal numWords_reg : BCD_ARRAY_TYPE(2 downto 0) := (others => (others => '0')); signal counter : integer range 0 to 3 := 3; signal next_txData : std_logic_vector(7 downto 0); signal next_txnow : std_logic; signal next_start : std_logic; signal next_rxdone : std_logic; signal next_counter : integer range 0 to 2; signal next_numWords_bcd : BCD_ARRAY_TYPE(2 downto 0) := (others => (others => '0')); signal next_rxData_reg : std_logic_vector(7 downto 0); signal rxData_reg : std_logic_vector(7 downto 0) := (others => '0'); signal sig_proof : std_logic := '0'; signal txData_reg : std_logic_vector(7 downto 0) := (others => '0'); signal numWordsDigit : integer range 0 to 2 := 2; signal next_numWordsDigit : integer range 0 to 2 := 0; signal data1 : std_logic_vector(7 downto 0); signal data2 : std_logic_vector(7 downto 0); signal data3 : std_logic_vector(7 downto 0); begin -- Main nextState logic updated on clock and reset process(clk, reset) begin if reset = '1' then curState <= IDLE; elsif rising_edge(clk) then curState <= nextState; end if; end process; process (seqDone, dataReady, txdone, byte, rxData, rxnow, curState) begin -- default values txnow <= '0'; rxdone <= '0'; start <= '0'; -- case curState is -------------------------------------------------------------------- when IDLE => if rxNow = '1' then rxData_reg <= rxData; nextState <= START_TRANSMIT; else nextState <= IDLE; end if; when START_TRANSMIT => txData_reg <= rxData; txNow <= '1'; rxDone <= '1'; nextState <= TRANSMIT_DATA; when TRANSMIT_DATA => if txDone = '1' then if txData_reg(7 downto 4) = "0011" then numWords_reg <= (data1, data2, data3); nextState <= IDLE1; -- if numWordsDigit = 1 then -- nextState <= numWords1; -- elsif numWordsDigit = 2 then -- nextState <= numWords2; -- elsif numWordsDigit = 3 then -- nextState <= numWords3; -- elsif rxData_reg = "01100001" or rxData_reg = "01000001" then -- CMD ANNN or aNNN# -- numWordsDigit <= 1; -- nextState <= IDLE; -- else -- nextState <= IDLE; -- end if; else nextState <= IDLE; end if; else nextState <= TRANSMIT_DATA; end if; when IDLE1 => if rxNow = '1' then rxData_reg <= rxData; nextState <= START_TRANSMIT; else nextState <= IDLE; end if; when START_TRANSMIT1 => txData_reg <= rxData; txNow <= '1'; rxDone <= '1'; nextState <= TRANSMIT_DATA; when TRANSMIT_DATA1 => if txDone = '1' then if txData_reg(7 downto 4) = "0011" then numWords_reg(1) <= txData_reg(3 downto 0); nextState <= IDLE2; else nextState <= IDLE; end if; else nextState <= TRANSMIT_DATA; end if; when IDLE2 => if rxNow = '1' then rxData_reg <= rxData; nextState <= START_TRANSMIT; else nextState <= IDLE; end if; when START_TRANSMIT2 => txData_reg <= rxData; txNow <= '1'; rxDone <= '1'; nextState <= TRANSMIT_DATA; when TRANSMIT_DATA2 => if txDone = '1' then if txData_reg(7 downto 4) = "0011" then numWords_reg(0) <= txData_reg(3 downto 0); nextState <= cmdA_proc; else nextState <= IDLE; end if; else nextState <= TRANSMIT_DATA; end if; -- when numWords1 => ---- if rxData_reg(7 downto 4) = "0011" then -- numWords_reg(2) <= "0000"; -- numWordsDigit <= numWordsDigit + 1; -- nextState <= IDLE; -- else -- nextState <= IDLE; -- end if; -- when numWords2 => -- numWords_reg(2) <= "0001"; -- numWordsDigit <= numWordsDigit + 1; -- nextState <= IDLE; -- if rxData_reg(7 downto 4) = "0011" then -- next_numWords_bcd(1) <= rxData_reg(3 downto 0); -- nextState <= IDLE; -- else -- nextState <= IDLE; -- end if; -- when numWords3 => -- numWords_reg(2) <= "0010"; -- nextState <= cmdA_proc; -- if rxData_reg(7 downto 4) = "0011" then -- next_numWords_bcd(0) <= rxData_reg(3 downto 0); -- nextState <= cmdA_proc; -- else -- nextState <= IDLE; -- end if; -------------------------------------------------------------------- when cmdA_proc => start <= '1'; -- if dataReady = '1' then -- txData_reg <= rxData; -- nextState <= START_TRANSMIT; -- else -- nextState <= IDLE; -- end if; -- when START_TRANSMIT => -- -- txData_reg <= numWords_first; -- txNow <= '1'; -- rxDone <= '1'; -- nextState <= TRANSMIT_DATA; -- when TRANSMIT_DATA => -- if txDone = '1' then -- if rxData = "01100001" or rxData = "01000001" then -- CMD ANNN or aNNN -- nextState <= cmdA_proc; -- else -- nextState <= IDLE; -- end if; -- nextState <= IDLE; -- else -- nextState <= TRANSMIT_DATA; -- end if; -------------------------------------------------------------------- if counter = 0 then next_start <= '1'; nextState <= byteFirstHalf; elsif rxNow = '1' and txdone = '1' then next_txData <= rxData; next_rxdone <= '1'; if rxData(7 downto 4) = "0011" then next_numWords_bcd(counter) <= rxData(3 downto 0); -- CHECK IF Numwords_bcd is latch free if counter > 0 then next_counter <= counter - 1; end if; nextState <= cmdA_proc; else nextState <= IDLE; -- Invalid start command end if; else nextState <= cmdA_proc; end if; when byteFirstHalf => if (dataReady = '1' and txDone = '1' and seqDone = '0') then next_txData <= hexConvert(byte(7 downto 4)); next_txNow <= '1'; nextState <= byteSecondHalf; else nextState <= byteFirstHalf; end if; when byteSecondHalf => if (dataReady = '1' and txDone = '1' and seqDone = '0') then next_txData <= hexConvert(byte(3 downto 0)); next_txNow <= '1'; nextState <= printSpaceCMDA; else nextState <= byteSecondHalf; end if; when printSpaceCMDA => if seqDone = '1' then nextState <= IDLE; elsif (dataReady = '1' and txDone = '1' and seqDone = '0') then next_txData <= "00100000"; next_txNow <= '1'; nextState <= byteFirstHalf; else nextState <= printSpaceCMDA; end if; when cmdP_proc => if txDone = '1' then next_txData <= hexConvert(dataResults(0)(7 downto 4)); next_txNow <= '1'; nextState <= pPeakSecondHalf; else nextState <= cmdP_proc; end if; when pPeakSecondHalf => if txDone = '1' then next_txData <= hexConvert(dataResults(3)(3 downto 0)); next_txNow <= '1'; nextState <= printSpaceCMDP; else nextState <= pPeakSecondHalf; end if; when printSpaceCMDP => if txDone = '1' then next_txData <= "00100000"; next_txNow <= '1'; nextState <= cmdP_print1; else nextState <= printSpaceCMDP; end if; when cmdP_print1 => if txdone = '1' then next_txData <= hexConvert(maxIndex(2)); next_txnow <= '1'; nextState <= cmdP_print2; else nextState <= cmdP_print1; end if; when cmdP_print2 => if txdone = '1' then next_txData <= hexConvert(maxIndex(1)); next_txnow <= '1'; nextState <= cmdP_print3; else nextState <= cmdP_print2; end if; when cmdP_print3 => if txDone = '1' then next_txData <= hexConvert(maxIndex(0)); next_txnow <= '1'; nextState <= IDLE; else nextState <= cmdP_print3; end if; when cmdL_proc => if txDone = '1' and seqDone = '1' then next_txData <= hexConvert(dataResults(0)(7 downto 4)); nextState <= l1nibble2; else nextState <= cmdL_proc; end if; when l1nibble2 => if txDone = '1' then next_txData <= hexConvert(dataResults(0)(3 downto 0)); next_txNow <= '1'; nextState <= l1nibbleSpace; else nextState <= l1nibble2; end if; when l1nibbleSpace => if txDone = '1' then next_txData <= "00100000"; next_txNow <= '1'; nextState <= l2nibble1; else nextState <= l1nibbleSpace; end if; when l2nibble1 => if txDone = '1' then next_txData <= hexConvert(dataResults(1)(7 downto 4)); next_txNow <= '1'; nextState <= l2nibble2; else nextState <= l2nibble1; end if; when l2nibble2 => if txDone = '1' then next_txData <= hexConvert(dataResults(1)(3 downto 0)); next_txNow <= '1'; nextState <= l2nibbleSpace; else nextState <= l2nibble2; end if; when l2nibbleSpace => if txDone = '1' then next_txData <= "00100000"; next_txNow <= '1'; nextState <= l3nibble1; else nextState <= l2nibbleSpace; end if; when l3nibble1 => if txDone = '1' then next_txData <= hexConvert(dataResults(2)(7 downto 4)); next_txNow <= '1'; nextState <= l3nibble2; else nextState <= l3nibble1; end if; when l3nibble2 => if txDone = '1' then next_txData <= hexConvert(dataResults(2)(3 downto 0)); next_txNow <= '1'; nextState <= l3nibbleSpace; else nextState <= l3nibble2; end if; when l3nibbleSpace => if txDone = '1' then next_txData <= "00100000"; next_txNow <= '1'; nextState <= l4nibble1; else nextState <= l3nibbleSpace; end if; when l4nibble1 => if txDone = '1' then next_txData <= hexConvert(dataResults(3)(7 downto 4)); next_txNow <= '1'; nextState <= l4nibble2; else nextState <= l4nibble1; end if; when l4nibble2 => if txDone = '1' then next_txData <= hexConvert(dataResults(3)(3 downto 0)); next_txNow <= '1'; nextState <= l4nibbleSpace; else nextState <= l4nibble2; end if; when l4nibbleSpace => if txDone = '1' then next_txData <= "00100000"; next_txNow <= '1'; nextState <= l5nibble1; else nextState <= l4nibbleSpace; end if; when l5nibble1 => if txDone = '1' then next_txData <= hexConvert(dataResults(4)(7 downto 4)); next_txNow <= '1'; nextState <= l5nibble2; else nextState <= l5nibble1; end if; when l5nibble2 => if txDone = '1' then next_txData <= hexConvert(dataResults(4)(3 downto 0)); next_txNow <= '1'; nextState <= l5nibbleSpace; else nextState <= l5nibble2; end if; when l5nibbleSpace => if txDone = '1' then next_txData <= "00100000"; next_txNow <= '1'; nextState <= l6nibble1; else nextState <= l5nibbleSpace; end if; when l6nibble1 => if txDone = '1' then next_txData <= hexConvert(dataResults(5)(7 downto 4)); next_txNow <= '1'; nextState <= l6nibble2; else nextState <= l6nibble1; end if; when l6nibble2 => if txDone = '1' then next_txData <= hexConvert(dataResults(5)(3 downto 0)); next_txNow <= '1'; nextState <= l6nibbleSpace; else nextState <= l6nibble2; end if; when l6nibbleSpace => if txDone = '1' then next_txData <= "00100000"; next_txNow <= '1'; nextState <= l7nibble1; else nextState <= l6nibbleSpace; end if; when l7nibble1 => if txDone = '1' then next_txData <= hexConvert(dataResults(6)(7 downto 4)); next_txNow <= '1'; nextState <= l7nibble2; else nextState <= l7nibble1; end if; when l7nibble2 => if txDone = '1' then next_txData <= hexConvert(dataResults(6)(3 downto 0)); next_txNow <= '1'; nextState <= IDLE; else nextState <= l7nibble2; end if; when others => nextState <= IDLE; end case; end process; numWords_bcd <= numWords_reg; txData <= txData_reg; end arch;
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