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-------------------ALU--------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_4bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
F : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0);
C_B : out STD_LOGIC);
end ALU_4bit;
architecture Behavioral of ALU_4bit is
signal result:STD_LOGIC_VECTOR (4 downto 0):="00000";
begin
process(A,B,F)
begin
CASE F is
when "000" =>
result<='0' & (A AND B);
when "001" =>
result<='0' & (A NAND B);
when "010" =>
result<='0' & (A OR B);
when "011" =>
result<='0' & (A XOR B);
when "100" =>
result<='0' & (A XNOR B);
when "101" =>
result<='0' & (A NOR B);
when "110" =>
result<=('0' & A)+('0' & B);
when others =>
if A<B then
result<='0'& (NOT B);
result<=result+1;
result<=('0'& A)+result;
result<=(NOT result)+1;
result<=(NOT(('0' & A) +('0' & (NOT B))+1)) +1;
else
result<=('0' & A)- ('0' & B);
end if;
end CASE;
end process;
Y<=result(3 downto 0);
C_B<=result(4);
end Behavioral;
-------------------Test Bench---------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ALU_4bit_tb IS
END ALU_4bit_tb;
ARCHITECTURE behavior OF ALU_4bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU_4bit
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
F : IN std_logic_vector(2 downto 0);
Y : OUT std_logic_vector(3 downto 0);
C_B : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := "0010";
signal B : std_logic_vector(3 downto 0) := "1111";
signal F : std_logic_vector(2 downto 0) := (others => '1');
--Outputs
signal Y : std_logic_vector(3 downto 0);
signal C_B : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU_4bit PORT MAP (
A => A,
B => B,
F => F,
Y => Y,
C_B => C_B
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
F<= F + 1;
wait for 25 ns;
-- insert stimulus here
end process;
END;
---------------------------USR---------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity USR is
Port ( Sin : in STD_LOGIC;
Pin : in STD_LOGIC_VECTOR (3 downto 0);
Sout : out STD_LOGIC;
Pout : out STD_LOGIC_VECTOR (3 downto 0);
Mode : in STD_LOGIC_VECTOR (1 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC);
end USR;
architecture Behavioral of USR is
SIGNAL temp:STD_LOGIC_VECTOR(3 downto 0):="0000";
begin
PROCESS(rst, clk, mode, Sin, Pin)
BEGIN
IF rst = '1' THEN
Pout <= "0000";
Sout <= '0';
ELSIF FALLING_EDGE(clk) THEN
CASE mode IS
WHEN "00" =>
temp(3 downto 1) <= temp(2 downto 0);
temp(0) <= Sin;
Sout <= temp(3);
Pout <= "0000";
WHEN "01" =>
temp(3 downto 1) <= temp(2 downto 0);
temp(0) <= Sin;
Pout <= temp;
Sout <= '0';
WHEN "10" =>
temp <= Pin;
Sout <= temp(3);
temp(3 downto 1) <= temp(2 downto 0);
Pout <= "0000";
WHEN OTHERS =>
Pout <= Pin;
Sout <= '0';
END CASE;
END IF;
END PROCESS;
end Behavioral;
---------------------Test Bench------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY USR_tb IS
END USR_tb;
ARCHITECTURE behavior OF USR_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT USR
PORT(
Sin : IN std_logic;
Pin : IN std_logic_vector(3 downto 0);
Sout : OUT std_logic;
Pout : OUT std_logic_vector(3 downto 0);
Mode : IN std_logic_vector(1 downto 0);
rst : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal Sin : std_logic := '0';
signal Pin : std_logic_vector(3 downto 0) := "1010";
signal Mode : std_logic_vector(1 downto 0) := (others => '0');
signal rst : std_logic := '0';
signal clk : std_logic := '1';
--Outputs
signal Sout : std_logic;
signal Pout : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: USR PORT MAP (
Sin => Sin,
Pin => Pin,
Sout => Sout,
Pout => Pout,
Mode => Mode,
rst => rst,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc_mode: process
begin
Mode<="00";
wait for 80 ns;
Mode<="01";
wait for 50 ns;
Mode<="10";
wait for 50 ns;
Mode<="11";
wait for 20 ns;
end process;
stim_proc_Sin:process
begin
wait for 10 ns;
Sin<='1';
wait for 10 ns;
Sin<='0';
wait for 10 ns;
Sin<='1';
wait for 10 ns;
Sin<='0';
wait for 10 ns;
Sin<= '0';
wait for 40 ns;
Sin<='1';
wait for 10 ns;
Sin<='0';
wait for 10 ns;
Sin<='1';
wait for 10 ns;
Sin<='0';
wait for 10 ns;
Sin<= '0';
wait ;
end process;
stim_proc_rst:process
begin
rst<='0';
wait for 300 ns;
rst<='1';
wait for 10 ns;
end process;
END;
-----------------------FIFO----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_4x8 is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0) := "00";
d_in : in STD_LOGIC_VECTOR (7 downto 0);
rd_wr : in STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
empty : out STD_LOGIC := '1';
full : out STD_LOGIC := '0');
end FIFO_4x8;
architecture FIFO_4x8_arch of FIFO_4x8 is
TYPE mem IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL memory : mem := (others=>(others=>'0'));
begin
PROCESS(rst, clk, addr, d_in, rd_wr)
begin
if rst = '1' then
d_out <= "00000000";
empty <= '1';
full <= '0';
memory <= (others=>(others=>'0'));
elsif falling_edge(clk) then
case rd_wr is
when '0' =>
d_out <= memory(conv_integer(addr));
empty <= '0';
full <= '1';
when others =>
memory(conv_integer(addr)) <= d_in;
empty <= '0';
if addr = "11" then
full <= '1';
else
full <= '0';
end if;
end case;
end if;
end process;
end FIFO_4x8_arch;
-----------------------------Test Bench------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
ENTITY FIFO_4x8_tb IS
END FIFO_4x8_tb;
ARCHITECTURE behavior OF FIFO_4x8_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FIFO_4x8
PORT(
rst : IN std_logic;
clk : IN std_logic;
addr : IN std_logic_vector(1 downto 0);
d_in : IN std_logic_vector(7 downto 0);
rd_wr : IN std_logic;
d_out : OUT std_logic_vector(7 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '1';
signal addr : std_logic_vector(1 downto 0) := (others => '0');
signal d_in : std_logic_vector(7 downto 0) := (others => '0');
signal rd_wr : std_logic := '0';
--Outputs
signal d_out : std_logic_vector(7 downto 0);
signal empty : std_logic;
signal full : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FIFO_4x8 PORT MAP (
rst => rst,
clk => clk,
addr => addr,
d_in => d_in,
rd_wr => rd_wr,
d_out => d_out,
empty => empty,
full => full
);
-- Clock process definitions
clk_process :process
begin
clk <= not(clk);
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '0';
wait for clk_period;
rst <= '1';
wait for clk_period;
rd_wr <= '1';
for address in 0 to 3 loop
addr <= std_logic_vector(to_unsigned(address, 2));
d_in <= std_logic_vector(to_unsigned(63*(address + 1), 8));
wait for clk_period*2;
end loop;
d_in <= std_logic_vector(to_unsigned(0, 8));
rd_wr <= '0';
for address in 0 to 3 loop
addr <= std_logic_vector(to_unsigned(address, 2));
wait for clk_period*2;
end loop;
end process;
END;
-------------------MODcounter------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mod25 is
Port ( rst : in STD_LOGIC;
pr : in STD_LOGIC;
clk : in STD_LOGIC;
dir : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (4 downto 0));
end mod25;
architecture mod25_arch of mod25 is
signal Qtemp : STD_LOGIC_VECTOR (4 downto 0) := "00000";
begin
process(rst,pr,clk,dir)
begin
if rst ='1' then
Qtemp <= (OTHERS =>'0');
elsif pr='1' then
Qtemp <= (OTHERS =>'1');
elsif falling_edge(clk) then
if dir = '1' then
if Qtemp < 24 then
Qtemp <= Qtemp + 1;
else
Qtemp <= "00000";
end if;
else
if Qtemp > 7 then
Qtemp <= Qtemp - 1;
else
Qtemp <= "11111";
end if;
end if;
end if;
end process;
Q<=Qtemp;
end mod25_arch;
----------------Test Bench-------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mod25_tb IS
END mod25_tb;
ARCHITECTURE behavior OF mod25_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mod25
PORT(
rst : IN std_logic;
pr : IN std_logic;
clk : IN std_logic;
dir : IN std_logic;
Q : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal pr : std_logic := '0';
signal clk : std_logic := '0';
signal dir : std_logic := '0';
--Outputs
signal Q : std_logic_vector(4 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mod25 PORT MAP (
rst => rst,
pr => pr,
clk => clk,
dir => dir,
Q => Q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc_dir: process
begin
dir <= not(dir);
wait for 320 ns;
end process;
stim_proc_rst: process
begin
wait for 680 ns;
rst <= '1';
wait for 40 ns;
rst <= '0';
wait;
end process;
stim_proc_pr: process
begin
wait for 750 ns;
pr <= '1';
wait for 40 ns;
pr <= '0';
wait;
end process;
END;
---------------------LCD---------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD_FSM is
Port ( rst : in std_logic; -- reset
clk_12Mhz : in std_logic; -- high freq. clock
lcd_rs : out std_logic; -- LCD RS control
lcd_en : out std_logic; -- LCD Enable
lcd_data : out std_logic_vector(7 downto 0)); -- LCD Data port
end LCD_FSM;
architecture Behavioral of LCD_FSM is
signal div : std_logic_vector(15 downto 0); --- delay timer 1
signal clk_fsm,lcd_rs_s: std_logic;
-- LCD controller FSM states
type state is (reset,func,mode,cur,clear,d0,d1,d2,d3,d4,hold);
signal ps1,nx : state;
signal dataout_s : std_logic_vector(7 downto 0); --- internal data command multiplexer
begin
----- clk divider ---------------------------------
process(rst,clk_12Mhz)
begin
if(rst = '1')then
div <= (others=>'0');
elsif( clk_12Mhz'event and clk_12Mhz ='1')then
div <= div + 1;
end if;
end process;
----------------------------------------------------
clk_fsm <= div(15);
----- Presetn state Register -----------------------
process(rst,clk_fsm)
begin
if(rst = '1')then
ps1 <= reset;
elsif (rising_edge(clk_fsm)) then
ps1 <= nx;
end if;
end process;
----- state and output decoding process
process(ps1)
begin
case(ps1) is
when reset =>
nx <= func;
lcd_rs_s <= '0';
dataout_s <= "00111000"; -- 38h
when func =>
nx <= mode;
lcd_rs_s <= '0';
dataout_s <= "00111000"; -- 38h
when mode =>
nx <= cur;
lcd_rs_s <= '0';
dataout_s <= "00000110"; -- 06h
when cur =>
nx <= clear;
lcd_rs_s <= '0';
dataout_s <= "00001100"; -- 0Ch curser at starting point of
when clear=>
nx <= d0;
lcd_rs_s <= '0';
dataout_s <= "00000001"; -- 01h
when d0 =>
lcd_rs_s <= '1';
dataout_s <= "01010000"; -- P ( Decimal = 80 , HEX = 50 )
nx <= d1;
when d1 =>
lcd_rs_s <= '1';
dataout_s <= "01001001"; -- I ( Decimal = 73 , HEX = 49 )
nx <= d2;
when d2 =>
lcd_rs_s <= '1';
dataout_s <= "01000011"; -- C ( Decimal = 67 , HEX = 43 )
nx <= d3;
when d3 =>
lcd_rs_s <= '1';
dataout_s <= "01010100"; -- T ( Decimal = 84 , HEX = 54 )
nx <= d4;
when d4 =>
lcd_rs_s <= '1';
dataout_s <= "00100000"; -- space ( Decimal = 32 , HEX = 20 )
nx <= hold;
when hold =>
lcd_rs_s <= '0';
dataout_s <= "00000000"; -- hold ( Decimal = 32 , HEX = 00 ) ,
nx <= hold;
when others=>
nx <= reset;
lcd_rs_s <= '0';
dataout_s <= "00000001"; -- CLEAR ( Decimal = 1 , HEX = 01 )
end case;
end process;
lcd_en <= clk_fsm;
lcd_rs <= lcd_rs_s;
lcd_data <= dataout_s;
end Behavioral;
------------------------Test Bench--------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LCD_Test IS
END LCD_Test;
ARCHITECTURE behavior OF LCD_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LCD_FSM
PORT(
rst : IN std_logic;
clk_12Mhz : IN std_logic;
lcd_rs : OUT std_logic;
lcd_en : OUT std_logic;
lcd_data : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk_12Mhz : std_logic := '0';
--Outputs
signal lcd_rs : std_logic;
signal lcd_en : std_logic;
signal lcd_data : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_12Mhz_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LCD_FSM PORT MAP (
rst => rst,
clk_12Mhz => clk_12Mhz,
lcd_rs => lcd_rs,
lcd_en => lcd_en,
lcd_data => lcd_data
);
-- Clock process definitions
clk_12Mhz_process :process
begin
clk_12Mhz <= '0';
wait for clk_12Mhz_period/2;
clk_12Mhz <= '1';
wait for clk_12Mhz_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 20 ns;
rst <= '0';
-- insert stimulus here
wait;
end process;
END;
-----------------js10_node----------------------------
// const num = process.argv[2];
// if (!number || isNaN(number) || number <= 0) {
// console.log("Please provide a valid positive number as an argument.");
// } else {
// console.log(`Multiplication Table for ${number}:\n`);
// for (let i = 1; i <= 10; i++) {
// console.log(`${number} x ${i} = ${number * i}`);
// }
// }
const readline = require('readline');
const rl = readline.createInterface({
input: process.stdin,
output: process.stdout
});
rl.question('Enter a number: ', (input) => {
const num = parseInt(input);
if (!isNaN(num) && num >= 1) {
console.log(`Multiplication Table for ${num}:\n`);
// for loop
console.log('using for loop');
for (let i = 1; i <= 10; i++) {
console.log(`${i} * ${num} = ${i * num}`);
}
// while loop
let j = 1;
console.log('using while loop');
while (j != 11) {
console.log(`${j} * ${num} = ${j * num}`);
j++;
}
// do while loop
let k = 1;
console.log('using do while loop');
do {
console.log(`${k} * ${num} = ${k * num}`);
k++;
} while (k != 11)
} else {
console.log('Please enter a valid number.');
}
rl.close();
});
--------------------js9_form---------------------------------
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<title>JS_9</title>
<!-- <link rel="stylesheet" href="js9.css">
<script src="js9.js"></script> -->
<style>
.box {
background-color: bisque;
padding: 10px;
margin-left: 500px;
margin-right: 500px;
margin-top: 100px;
border-style: solid;
border-color: black;
text-align: center;
}
.welcomeMessage{
margin-top: -10%;
margin-bottom: -10%;
margin-left: -10%;
margin-right: -10%;
}
</style>
<script>
function validate_form() {
let name = document.getElementById("n").value;
let mobile = document.getElementById("m").value;
let address = document.getElementById("a").value;
let email = document.getElementById("e").value;
if (name.length === 0) {
document.getElementById("no").innerHTML = "Empty";
return false;
}
else {
let name_reg = /^[A-Za-z\s]+$/;
if (!name.match(name_reg)) {
document.getElementById("no").innerHTML = "Invalid Input";
return false;
}
else {
document.getElementById("no").innerHTML = "";
}
// let f = 0;
// for(let i=0; i<name.length; i++){
// if((name[i]>='A' && name[i]<='Z') || (name[i]>='a' && name[i]<='z') || name[i]==' ') continue;
// else{
// f = 1;
// break;
// }
// }
// if(f) document.getElementById("no").innerHTML = "Invalid Input";
}
if (mobile.length === 0) {
document.getElementById("mo").innerHTML = "Empty";
return false;
}
else {
// if(mobile.length !== 10) document.getElementById("mo").innerHTML = "Invalid Input";
let mobile_reg = /^[0-9]{10}$/;
if (!mobile.match(mobile_reg)) {
document.getElementById("mo").innerHTML = "Invalid Input";
return false;
}
else {
document.getElementById("mo").innerHTML = "";
// return false;
}
}
if (address.length === 0) {
document.getElementById("ao").innerHTML = "Empty";
return false;
}
else {
document.getElementById("ao").innerHTML = "";
}
if (email.length === 0) {
document.getElementById("eo").innerHTML = "Empty";
return false;
}
else {
// let email_reg = /^[a-zA-Z0-9.!#$%&'*+/=?^_`{|}~-]+@[a-zA-Z0-9-]+(?:\.[a-zA-Z0-9-]+)*$/;
let email_reg = /^[a-z\.0-9_-]+@[a-z]+\.[a-z]{2,4}$/;
if (!email.match(email_reg)) {
document.getElementById("eo").innerHTML = "Invalid Input";
return false;
}
else {
document.getElementById("eo").innerHTML = "";
// window.location.href = 'newpg.html'; // redirects to new html page
// If all validations pass, display welcome message
document.getElementById("welcomeName").textContent = name;
document.getElementById("myform").style.display = "none";
document.getElementById("welcomeMessage").style.display = "block";
return false; // to prevent form from getting submitted
}
// let f1 = 0;
// if(email[0]>=0 && email[0]<=9) f1 = 1;
// let at = email.indexof('@');
// let dotcom = email.lastindexof('.com');
// let dotin = email.lastindexof('.in');
// let dotedu = email.lastindexof('.edu');
// if(at<1 || at==-1 || dotcom==-1 || dotin==-1 || dotedu==-1 || at>dotcom || at>dotin || at>dotedu) document.getElementById("eo").innerHTML = "Invalid Input";
}
}
</script>
</head>
<body>
<div class="box">
<form id="myform" onsubmit="return validate_form()">
<h2>Employee Info Form</h2>
<label>Name : </label>
<input type="text" id="n"> <br><br>
<p id="no"></p> <br><br>
<label>Mobile No. : </label>
<input type="text" id="m"> <br><br>
<p id="mo"></p> <br><br>
<label>Address : </label>
<input type="text" id="a"> <br><br>
<p id="ao"></p> <br><br>
<label>email id : </label>
<input type="text" id="e"> <br><br>
<p id="eo"></p> <br><br>
<label>Gender : </label>
<select name="Gender" id="">
<option value="Male">Male</option>
<option value="Female">Female</option>
<option value="Other">Other</option>
</select><br><br>
<input type="submit" value="Submit">
<input type="reset" value="Reset">
<!-- <button id="Submit" onclick="validate_form()">Submit</button>
<button id="Reset" onclick="reset_form()">Reset</button> -->
</form>
</div>
<div id="welcomeMessage" style="display: none">
<h2>Congratulations!</h2>
<p>
Welcome, <span id="welcomeName"></span>! Your information has been
successfully submitted.
</p>
</div>
</body>
</html>
----------------------------js5_counter--------------------------------------------
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<title>Up Time Counter</title>
<style>
body {
font-family: 'Arial', sans-serif;
text-align: center;
margin-top: 50px;
}
#uptime {
font-size: 24px;
font-weight: bold;
color: #333;
}
#startTime {
font-size: 16px;
color: #777;
margin-top: 10px;
}
#startButton {
padding: 10px 20px;
font-size: 16px;
cursor: pointer;
}
</style>
</head>
<body>
<h1>Up Time Counter</h1>
<div id="uptime">0 seconds</div>
<div id="startTime"></div>
<button id="startButton" onclick="startCounting()">Start Counting</button>
<script>
var startTime;
function startCounting() {
// Set the start time when the button is clicked
startTime = new Date();
document.getElementById('startTime').innerText = 'Started at: ' + startTime.toLocaleString();
// Update the uptime every second
setInterval(updateUptime, 1000);
}
function updateUptime() {
// Check if the start time is defined
if (!startTime) {
return;
}
// Get the current time
var currentTime = new Date();
// Calculate the time difference since the page was loaded
var timeDifference = currentTime - startTime;
// Convert the time difference to seconds
var uptimeInSeconds = Math.floor(timeDifference / 1000);
// Update the uptime display
document.getElementById('uptime').innerText = uptimeInSeconds + ' seconds';
}
</script>
</body>
</html>
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