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module N_bit_register #(parameter WIDTH = 4) (
    input clk,
    input [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
);
    always @(posedge clk) begin
        q <= d;
    end
endmodule

module pipelined_carry_lookahead_adder #(parameter WIDTH = 4) (
    input clk,
    input [WIDTH-1:0] i_add1,
    input [WIDTH-1:0] i_add2,
    output reg [WIDTH:0] o_result
);
    wire [WIDTH-1:0] w_G, w_P, w_SUM_stage1, w_SUM_stage2;
    wire [WIDTH:0] w_C_stage1, w_C_stage2;
    reg [WIDTH:0] w_C;

    // Stage 1: Full Adders
    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i + 1) begin
            always @(*) begin
                w_SUM_stage1[i] = i_add1[i] ^ i_add2[i] ^ w_C[i];
            end
        end
    endgenerate

    // Register to hold intermediate sum values
    N_bit_register #(WIDTH) reg_stage1 (.clk(clk), .d(w_SUM_stage1), .q(w_SUM_stage2));

    // Stage 2: Generate and Propagate Terms
    generate
        for (i = 0; i < WIDTH; i = i + 1) begin
            assign w_G[i] = i_add1[i] & i_add2[i];
            assign w_P[i] = i_add1[i] | i_add2[i];
        end
    endgenerate

    // Stage 3: Carry Terms
    always @(*) begin
        w_C[0] = 1'b0; // no carry input on first adder
        for (i = 0; i < WIDTH; i = i + 1) begin
            w_C[i + 1] = w_G[i] | (w_P[i] & w_C[i]);
        end
    end

    // Register to hold intermediate carry values
    N_bit_register #(WIDTH) reg_stage2 (.clk(clk), .d(w_C[WIDTH-1:0]), .q(w_C_stage2[WIDTH-1:0]));

    always @(posedge clk) begin
        w_C_stage2[WIDTH] <= w_G[WIDTH-1] | (w_P[WIDTH-1] & w_C_stage2[WIDTH-1]);
        o_result <= {w_C_stage2[WIDTH], w_SUM_stage2}; // Verilog Concatenation
    end

endmodule
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