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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Hardware_transfer_logic_circuit is
    Port ( B : in  STD_LOGIC_VECTOR(3 downto 0);
			  Clr : in STD_LOGIC;
			  Clk : in STD_LOGIC;
           Load : in  STD_LOGIC;
			  RCO: out STD_LOGIC;
           Output : inout  STD_LOGIC_VECTOR(3 downto 0));
end Hardware_transfer_logic_circuit;

architecture Structural of Hardware_transfer_logic_circuit is
	component four_bit_counter is
			Port ( CLR : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Vcc : in  STD_LOGIC;
           GND : in  STD_LOGIC;
           ENP : in  STD_LOGIC;
           ENT : in  STD_LOGIC;
           LOAD : in  STD_LOGIC;
			  INPUT: in STD_LOGIC_VECTOR(3 downto 0);
			  RCO : out  STD_LOGIC;
			  OUTPUT: inout STD_LOGIC_VECTOR(3 downto 0));
	end component;
	
	component four_bit_full_adder is
		port( A:IN STD_LOGIC_VECTOR(3 downto 0);
				B: IN STD_LOGIC_VECTOR(3 downto 0);
				Cin : IN STD_LOGIC;
				Sum: OUT STD_LOGIC_VECTOR(3 downto 0);
				Cout: OUT STD_LOGIC;
				Vcc: IN STD_LOGIC;
				Gnd: IN STD_LOGIC);
	end component;
	
	signal sum_temp:STD_LOGIC_VECTOR(3 downto 0);
	signal high:STD_LOGIC:='1';
	signal low:STD_LOGIC:='0';
begin
	HTL0: four_bit_full_adder port map(A=>Output,B=>B,Cin=>'0',Sum=>sum_temp,Vcc=>high,Gnd=>low);
   HTL1: four_bit_counter port map(CLR=>Clr,CLK=>Clk,Vcc=>high,GND=>low,ENP=>high,ENT=>high,LOAD=>Load,INPUT=>sum_temp,OUTPUT=>Output,RCO=>RCO);


end Structural;