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`timescale 1ns / 1ps
module LabL5;
// Declare inputs as reg and outputs as wire
reg a, b, cin;
wire z, cout;
// Instantiate the 1-bit adder
yAdder1 my_adder(z, cout, a, b, cin);
// Testbench variables
reg [2:0] input_combination; // To iterate through all combinations of a, b, cin
reg [2:0] expected_result;
integer pass_count, fail_count;
// Test the adder
initial begin
// Initialize counters
pass_count = 0;
fail_count = 0;
// Display header
$display("a b cin | Expected z cout | Actual z cout Result");
$display("-----------------------------------------------|----------------- ----------- ------");
// Exhaustive testing
for (input_combination = 0; input_combination < 8; input_combination = input_combination + 1) begin
{a, b, cin} = input_combination;
// Calculate expected sum and carry-out
expected_result = a + b + cin;
case (expected_result)
3'b000: begin
expected_result = 3'b000; // z = 0, cout = 0
end
3'b001: begin
expected_result = 3'b001; // z = 1, cout = 0
end
3'b010: begin
expected_result = 3'b010; // z = 0, cout = 1
end
3'b011: begin
expected_result = 3'b011; // z = 1, cout = 1
end
3'b100: begin
expected_result = 3'b001; // z = 0, cout = 1 (overflow, treated as 2 bits)
end
3'b101: begin
expected_result = 3'b010; // z = 1, cout = 1 (overflow, treated as 2 bits)
end
3'b110: begin
expected_result = 3'b011; // z = 0, cout = 1 (overflow, treated as 2 bits)
end
3'b111: begin
expected_result = 3'b011; // z = 1, cout = 1 (overflow, treated as 2 bits)
end
endcase
#10; // Wait for 10 time units
// Check if the output is as expected
if ({z, cout} !== expected_result[1:0]) begin
fail_count = fail_count + 1;
$display("%b %b %b | %b %b | %b %b FAIL", a, b, cin, expected_result[1], expected_result[0], z, cout);
end else begin
pass_count = pass_count + 1;
end
end
// Display summary
$display("-----------------------------------------------|----------------- ----------- ------");
$display("Total Tests: %d", pass_count + fail_count);
$display("Passed: %d", pass_count);
$display("Failed: %d", fail_count);
// Finish simulation
$finish;
end
endmodule
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