Untitled
unknown
verilog
a year ago
585 B
0
Indexable
Never
module REG4( A0,A1,A2,A3,CLK, Q1,Q2,Q3,Q4 ); input wire A0,A1,A2,A3,CLK; output reg Q1,Q2,Q3,Q4; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_5; assign SYNTHESIZED_WIRE_0 = 1; assign SYNTHESIZED_WIRE_5 = CLK & SYNTHESIZED_WIRE_0; always@(posedge SYNTHESIZED_WIRE_5) begin begin Q1 <= A0; end end always@(posedge SYNTHESIZED_WIRE_5) begin begin Q2 <= A1; end end always@(posedge SYNTHESIZED_WIRE_5) begin begin Q3 <= A2; end end always@(posedge SYNTHESIZED_WIRE_5) begin begin Q4 <= A3; end end endmodule