DESTop
unknown
verilog
2 years ago
676 B
4
Indexable
module DESTop ( input wire [0:31] MessageH, input wire [0:31] MessageL, input wire [0:31] KeyH, input wire [0:31] KeyL, input wire enable_i, input wire clk_i, output reg [0:31] OutputH, output reg [0:31] OutputL, output wire done_o ); reg [0:63] Message; reg [0:63] Key; wire [0:63] Output; DES DesGen ( .input_i(Message), .key_i(Key), .enable_i(enable_i), .clk_i(clk_i), .output_o(Output), .done_o(done_o) ); always @ * begin OutputH = Output[0:31]; OutputL = Output[32:63]; Message = {MessageH, MessageL}; Key = {KeyH, KeyL}; end endmodule
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