Untitled

module ex1(input logic [3:0] seg_in, output logic [6:0] seg_out);
int segment[10] = {0b01000000, 0b01111001, 0b00100100, 0b00110000, 
                   0b00011001, 0b00010010, 0b00000010, 0b01111000, 
                   0b00000000, 0b00010000};
	always_comb begin
		case (seg_in)
			0: seg_out = 7'b100_0000;
			1: seg_out = 7'b111_1001;
			2: seg_out = 7'b010_0100;
			3: seg_out = 7'b011_0000;
			4: seg_out = 7'b001_1001;
			5: seg_out = 7'b001_0010;
			6: seg_out = 7'b000_0010;
			7: seg_out = 7'b111_1000;
			8: seg_out = 7'b000_0000;
			9: seg_out = 7'b001_0000;
			10: seg_out = 7'b000_1000;
			11: seg_out = 7'b000_0011;
			12: seg_out = 7'b010_0111;
			13: seg_out = 7'b010_0001;
			14: seg_out = 7'b000_0110;
			15: seg_out = 7'b000_01110;
			default: begin 
			end
		endcase
	end
endmodule