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Verilog Codes
Half Adder
module ha(a,b,sum,cout);
input a,b;
output sum,cout;
xor(sum,a,b);
and(cout,a,b);
endmodule

Full Adder
module fa(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire x,y,z;
xor (x,a,b);
and(y,a,b);
xor (sum,x,c);
and(z,x,c);
or(cout,y,z);
endmodule

Half Sub
module hs(a,b,diff,borrow);
input a,b;
output diff,borrow;
wire w1;
xor(diff,a,b);
not(w1,a);
and(borrow,w1,b);
endmodule

Full Sub
module fs(a,b,cin,diff,borrow);
input a,b,cin;
output diff,borrow;
wire x,y,z,p,q;
xor (x,a,b);
not(y,a);
and(z,y ,b);
xor (diff,x,c);
not(p,x);
and(q,p,c);
or(borrow,z,q);
endmodule



4 Bit RCA
module rca4b(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire [2:0]c;

fa fa0(a[0],b[0],cin,s[0],c[0]);
fa fa1(a[1],b[1],c[0],s[1],c[1]);
fa fa2(a[2],b[2],c[1],s[2],c[2]);
fa fa3(a[3],b[3],c[2],s[3],cout);
endmodule

4 Bit RCA Test Bench
module rca4b_tb;
reg [3:0]a,b;
reg cin;
wire [3:0]s;
wire cout;

rca4b rca(.a(a),.b(b),.cin(cin),.s(s),.cout(cout));
initial
begin
 a=5;b=5;cin=0;
#100; a=5;b=5;cin=1;
#100; a=8;b=5;cin=0;
#100; a=8;b=5;cin=1;
#100;
end
endmodule

4x1 MUX
module MUX_04_to_1g(S0, S1, DO, D1, D2, D3, Y);
input S0, S1, DO, D1, D2, D3;
output Y;

wire nS0, nS1, w1, w2, w3, w4;
not n1 (nS0, S0);
not n2(nS1, S1);

and g1 (w1, nS0, nS1, D0);
and g2 (w2, nS0, S1, D1):
and g3 (w3, S0, nS1, D2);
and g4 (w4, S0, S1, D3);
or g5 (Y, w1, w2, w3, w4);
endmodule

1x4 demux

module DEMUX_04_to_1g(S0, S1, D,DO, D1, D2, D3);
input S0, S1,D;
output DO, D1, D2, D3;

wire nS0, nS1;
not n1 (nS0, S0);
not n2(nS1, S1);

and g1 (D0, nS0, nS1, D);
and g2 (D1, S0, nS1, D);
and g3 (D2, nS0, S1, D);
and g4 (D3, S0, S1, D);
endmodule





SR Flip Flop
module sr_ff(s,r,clk,q,qb);
input s,r,clk;
output q,qb;
reg q,qb;
always @ (posedgeclk)
begin

case({s,r})
2'b00 : q=q;
2'b01 : q=0;
2'b10 : q=1;
2'b11 : q=1'bx;
endcase
end
endmodule

SR Flip Flop Test Bench
module sr_ff_tb;
reg s,r,clk;
wire q,qb;

sr_ffsr(.q(q),.qb(qb),.s(s),.r(r),.clk(clk));

always #100 clk=~clk;
initial
begin
clk=1;
#200 s=1;r=0;
#200 s=0;r=0;
#200 s=0;s=1;
#200 s=1;r=1;
end
endmodule

JK FLIP FLOP
module JKFF(J,K,Q,QB,CLK);
input J,K,CLK;
output Q,QB;
reg Q,QB;
always @(posedge CLK)
begin case({J,K})
	2'b00:Q=Q; 
	2'b01:Q=0;
	2'b10:Q=1;
	2'b11:Q=~Q;
endcase
QB=~Q;
end 
endmodule

//TB
module JKFF_tb;
reg J,K,CLK;
wire Q,QB;

JKFF uut(.J(J),.K(K),.CLK(CLK),.Q(Q),.QB(QB));
always #100 CLK=~CLK;
initial begin
	CLK=1;
#100 J=0; K=0;
#100 J=0; K=1;
#100 J=1; K=0;
#100 J=1; K=1;
end
endmodule

D FLIP FLOP
module D_FF(Q,QB,D,CLK);
input D,CLK;
output Q,QB;
reg Q,QB;
always @(posedge CLK)
begin
Q=D;
QB=~Q;
end
endmodule


module D_FF_TB;
reg D;
reg CLK;
wire Q;
wire QB;
D_ffuut (.Q(Q),.QB(QB),.D(D),.CLK(CLK));
always#100CLK=~CLK;
initial begin
//initialize Inputs
CLK=1;
#200 D=1;
#200 D=0;
end
endmodule

module T_FF(Q,QB,T,CLK); 
input T,CLK;
 output Q,QB;
 reg Q=0,QB;
 always @(posedge CLK)
 begin
 case(T)
 1'b0:Q=Q;
 1'b1:Q=~Q;
 Endcase
 QB=~Q;
 End
 endmodule

module T_FF_TB; 
 reg T;
 reg CLK;
 wire Q;
 wire QB;
 T_FF uut ( .Q(Q), .QB(QB), .T(T), .CLK(CLK) );
 always #100 CLK=~CLK;
 initial begin 
 CLK=1;
 #200 T=0;
 #200 T=1;
 #200 T=0;
 #200 T=1;
 End
 Endmodule

4BITMAGCOMP:verilog code

module magnitude_comparator_g(A, B, Greater, Lesser, Equal);
input [3:0]A, B;
output Greater, Lesser, Equal;
wire [3:0]nA, nB;
wire x0, x1, x2, x3, 10, 11,12, 13, g0, g1, g2, g3;

not (nA[0], A[0]) ;
not (nA[1] , A[1]);
not ( nA[2] A[2]);
not [ nA[3] A[3]);

not ( nB[0] , B[0]);
not ( nB[1], B[1]) ;
not (nB[2], B[2]);
not (nB[3], B[3]);


xnor [x0 ,A[0],B[0] );
xnor (x1, A[1], B[1]);
xnor ( x2,A[2],B[2]);
xnor ( x3,A[3],B[3]);
and (Equal, x0, x1, x2, x3);

and (10, nA[0] , B[0], x3, x2, x1);
and (11, nA[1], B[1], x3, x2);
and (12, nA [2], B[2], x3);
and (13, nA[3], B[3]);
or (Lesser, 10, 11, 12, 13);

and (g0, A[0], B[0], x3, x2, x1);
and (g1, A[1], B[1], x3, x2);
and (g2, A[2], B[2], x3);
and (g3, A[3], B[3]);
or (Greater, g0, g1, g2, g3);

endmodule