Untitled

module moore(output reg out, input x,input clk, input rst_n);
parameter[1:0] reset=2'b00,got1=2'b01,got10=2'b10,got101=2'b11;
reg[1:0] state,next;
always @ (posedge clk, posedge rst_n)
begin
if(rst_n == 1)
state<=reset;
else
state<=next;
end
always@(state or x)
begin 
out = 1'b0;
case(state)
reset:
begin
if(x==1'b1)
next=got1;
else
next=reset;
end
got1:
begin
if(x==1'b0)
next=got10;
else
next=got1;
end
got10:
begin
if (x==1'b1)
next=got101;
else
next=reset;
end
got101:
begin
out=1'b1;
if(x==1'b0)
next=got10;
else
next=got1;
end
default:
begin
next=reset;
end
endcase
end
endmodule