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Behavioral Modelling module JK_FF(Q,QB,J,K,CLK); input J,K,CLK; output Q,QB; reg Q,QB; always @(posedge CLK) begin case({J,K}) 2'b00:Q=Q; 2'b01:Q=0; 2'b10:Q=1; 2'b11:Q=~Q; endcase QB=~Q; end endmodule Test Bench module JK_FF_TB; reg J; reg K; reg CLK; wire Q; wire QB; JK_FF uut (.Q(Q), .QB(QB), .J(J), .K(K), .CLK(CLK)); always #100 CLK=~CLK; initial begin CLK=1; #200 J=1;K=0; #200 J=0; K=0; #200 J=0; K=1; #200 J=1; K=1; end endmodule Behabioral modelling module D_FF(Q,QB,D,CLK); input D,CLK; output Q,QB; reg Q,QB; always @(posedge CLK) begin Q=D; QB=~Q; end endmodule Test Bench module D_FF_TB; reg D; reg CLK; wire Q; wire QB; D_FF uut (.Q(Q), .QB(QB), .D(D), .CLK(CLK)); always #100 CLK=~CLK; initial begin CLK=1; #200 D=1; #200 D=0; end endmodule Gate modeling module srff_gate(q, qbar, s, r, clk); input s,r,clk; output q, qbar; wire nand1_out; // output of nand1 wire nand2_out; // output of nand2 nand (nand1_out,clk,s); nand (nand2_out,clk,r); nand (q,nand1_out,qbar); nand (qbar,nand2_out,q); endmodule Behavioral Modelling module srff(clk,s,r,q); input clk,s,r; output reg q; always @ (posedge clk) begin case({s,r}) 2'b00: q <= q; 2'b01: q <= 0; 2'b10: q <= 1; 2'b11: q <= 1'bx; default: q <= q; endcase end endmodule Test Bench module dff_test; reg S,R, CLK; wire Q, QBAR; srff_behavior dut(.q(Q), .qbar(QBAR), .s(S), .r(R), .clk(CLK)); // instantiation by port name. $monitor("simtime = %g, CLK = %b, S = %b, R = %b, Q = %b, QBAR = %b", $time, CLK, S,R, Q, QBAR); initial begin clk=0; forever #10 clk = ~clk; end initial begin S= 1; R= 0; #100; S= 0; R= 1; #100; S= 0; R= 0; #100; S= 1; R=1; end endmodule Behavioral Modelling module T_FF(Q,QB,T,CLK); input T,CLK; output Q,QB; reg Q=0,QB; always @(posedge CLK) begin case(T) 1'b0:Q=Q; 1'b1:Q=~Q; endcase QB=~Q; end endmodule Test Bench module T_FF_TB; reg T; reg CLK; wire Q; wire QB; T_FF uut (.Q(Q), .QB(QB), .T(T),.CLK(CLK)); always #100 CLK=~CLK; initial begin CLK=1; #200 T=0; #200 T=1; #200 T=0; #200 T=1; end endmodule